Data Sheet
6
PCA9546A
SCPS148G –OCTOBER 2005–REVISED MAY 2016
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C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
MIN MAX UNIT
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 1)
t
sdh
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C serial-data hold time 0
(1)
ns
t
icr
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C input rise time 1000 ns
t
icf
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C input fall time 300 ns
t
ocf
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C output fall time 10-pF to 400-pF bus 300 ns
t
buf
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C bus free time between stop and start 4.7 µs
t
sts
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C start or repeated start condition setup 4.7 µs
t
sth
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C start or repeated start condition hold 4 µs
t
sps
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C stop condition setup 4 µs
t
vdL(Data)
Valid data time (high to low)
(2)
SCL low to SDA output low valid 1 µs
t
vdH(Data)
Valid data time (low to high)
(2)
SCL low to SDA output high valid 0.6 µs
t
vd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
1 µs
C
b
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C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2) C
b
= total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 1)
MIN MAX UNIT
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C BUS—FAST MODE
f
scl
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C clock frequency 0 400 kHz
t
sch
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C clock high time 0.6 µs
t
scl
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C clock low time 1.3 µs
t
sp
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C spike time 50 ns
t
sds
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C serial-data setup time 100 ns
t
sdh
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C serial-data hold time 0
(1)
ns
t
icr
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C input rise time 20 + 0.1C
b
(2)
300 ns
t
icf
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C input fall time 20 + 0.1C
b
(2)
300 ns
t
ocf
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C output fall time 10-pF to 400-pF bus 20 + 0.1C
b
(2)
300 ns
t
buf
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C bus free time between stop and start 1.3 µs
t
sts
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C start or repeated start condition setup 0.6 µs
t
sth
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C start or repeated start condition hold 0.6 µs
t
sps
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C stop condition setup 0.6 µs
t
vdL(Data)
Valid data time (high to low)
(3)
SCL low to SDA output low valid 1 µs
t
vdH(Data)
Valid data time (low to high)
(3)
SCL low to SDA output high valid 0.6
t
vd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
1 µs
C
b
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C bus capacitive load 400 pF