Data Sheet

ManualsBrandsOSEPP ELECTRONICS ManualsOSEPP PartsOSEPP I2C Expansion Shield

PCA9546A

Slaves A0, A1...AN

Slaves B0, B1...BN

Slaves C0, C1...CN

Slaves D0, D1...DN

I2C or SMBus

Master

(e.g. Processor)

SDA

SCL

SD0

SC0

Channel 0

Channel 1

Channel 2

Channel 3

RESET

SD1

SC1

SD2

SC2

SD3

SC3

GND

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

PCA9546A

SCPS148G –OCTOBER 2005–REVISED MAY 2016

PCA9546A Low Voltage 4-Channel I

C and SMBus Switch with Reset Function

1 Features

• 1-of-4 Bidirectional Translating Switches

• I

C Bus and SMBus Compatible

• Active-Low Reset Input

• Three Address Pins, Allowing up to Eight

PCA9546A Devices on the I

C Bus

• Channel Selection Via I

C Bus, in Any

Combination

• Power-up With All Switch Channels Deselected

• Low R

Switches

• Allows Voltage-Level Translation Between

1.8-V, 2.5-V, 3.3-V, and 5-V Buses

• No Glitch on Power-up

• Supports Hot Insertion

• Low Standby Current

• Operating Power-Supply Voltage Range of 2.3 V

to 5.5 V

• 5.5 V Tolerant Inputs

• 0 to 400-kHz Clock Frequency

• Latch-Up Performance Exceeds 100 mA Per

JESD 78

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

2 Applications

• Servers

• Routers (Telecom Switching Equipment)

• Factory Automation

• Products With I

C Slave Address Conflicts

(for example. Multiple, Identical Temp Sensors)

3 Description

The PCA9546A is a quad bidirectional translating

switch controlled via the I

C bus. The SCL/SDA

upstream pair fans out to four downstream pairs, or

channels. Any individual SCn/SDn channel or

combination of channels can be selected, determined

by the contents of the programmable control register.

An active-low reset (RESET) input allows the

PCA9546A to recover from a situation in which one of

the downstream I

C buses is stuck in a low state.

Pulling RESET low resets the I

C state machine and

causes all the channels to be deselected, as does the

internal power-on reset function.

The pass gates of the switches are constructed such

that the V

pin can be used to limit the maximum

high voltage, which will be passed by the PCA9546A.

This allows the use of different bus voltages on each

pair, so that 1.8-V, 2.5-V, or 3.3-V parts can

communicate with 5-V parts without any additional

protection. External pull-up resistors pull the bus up

to the desired voltage level for each channel. All I/O

pins are 5.5-V tolerant.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

PCA9546A TSSOP (16) 5.00 mm x 4.40 mm

Simplified Application Diagram

Summary of content (38 pages)

PAGE 1
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 PCA9546A Low Voltage 4-Channel I2C and SMBus Switch with Reset Function 1 Features 2 Applications • • • • • • • • 1 • • • • • • • • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Active-Low Reset Input Three Address Pins, Allowing up to Eight PCA9546A Devices on the I2C Bus Channel Selection Via I2C Bus, in Any Combination Power-
PAGE 2
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications..............................................
PAGE 3
PCA9546A www.ti.
PAGE 4
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage (2) MIN MAX UNIT –0.5 7 V VI Input voltage 7 V II Input current –0.
PAGE 5
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 6.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR TEST CONDITIONS Power-on reset voltage (2) No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.6 2.1 5V 3.6 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 μA 2.6 3.3 V 3 V to 3.6 V IOL VOL = 0.4 V SCL, SDA 2.3 V to 5.5 V VOL = 0.6 V 1.6 2.
PAGE 6
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com I2C Interface Timing Requirements (continued) over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) MIN 2 0 MAX (1) UNIT tsdh I C serial-data hold time ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns 2 10-pF to 400-pF bus ns tocf I C output fall time tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.
PAGE 7
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 6.6 Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tWL trst Pulse duration, RESET low (1) tREC(STA) (1) MIN MAX 6 RESET time (SDA clear) ns 500 Recovery time from RESET to start UNIT 0 ns ns trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition.
PAGE 8
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.
PAGE 9
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 Parameter Measurement Information (continued) Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL Figure 2.
PAGE 10
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com 8 Detailed Description 8.1 Overview The PCA9546A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well as any combination of the four channels.
PAGE 11
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 8.3 Feature Description The PCA9546A is a 4-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100 kHz) and Fast-Mode (400 kHz) operation. The PCA9546A features I2C control using a single 8-bit control register in which the four least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow.
PAGE 12
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com Programming (continued) Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 4). SDA SCL S P Start Condition Stop Condition Figure 4.
PAGE 13
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 Programming (continued) Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for ACK Start Condition Figure 6. Acknowledgment on the I2C Bus Data is transmitted to the PCA9546A control register using the write mode shown in Figure 7.
PAGE 14
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com 8.6 Control Register 8.6.1 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9546A is shown in Figure 9. To conserve power, no internal pull-up resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 0 1 A2 A1 A0 R/W Hardware Selectable Fixed Figure 9.
PAGE 15
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 Control Register (continued) Table 1.
PAGE 16
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com Typical Application (continued) VDPUM = 2.3 V to 5.5 V VCC = 3.3 V VDPU0 = 2.3 V to 5.5 V 16 VCC I2C/SMBus Master SDA SCL 15 14 3 SDA SD0 SCL SC0 4 Channel 0 5 VDPU1 = 2.3 V to 5.5 V RESET SD1 6 SC1 7 Channel 1 VDPU2 = 2.3 V to 5.5 V PCA9546A SD2 SC2 9 Channel 2 10 VDPU3 = 2.3 V to 5.5 V 13 2 1 8 A2 A1 A0 SD3 GND SC3 11 Channel 3 12 Copyright © 2016, Texas Instruments Incorporated Figure 11.
PAGE 17
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 Typical Application (continued) 9.2.1 Design Requirements The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9546A. These pins may be tied directly to GND or VCC in the application. If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the master side will be the sum of the currents through all pull-up resistors, Rp.
PAGE 18
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com Typical Application (continued) 9.2.3 PCA9546A Application Curves 25 5 Standard-mode Fast-mode 4.5 Maximum 20 Typical 3.5 Rp(max) (kOhm) Vpass (V) 4 3 2.5 2 Minimum 1.5 1 2 2.5 3 3.5 4 4.5 5 10 5 5.5 0 0 VCC (V) Space spacespace 15 Space spacespace 50 100 150 200 250 Cb (pF) Standard-mode (fSCL= 100 kHz, tr = 1 µs) Figure 12.
PAGE 19
PCA9546A www.ti.com SCPS148G – OCTOBER 2005 – REVISED MAY 2016 10 Power Supply Recommendations The operating power-supply voltage range of the PCA9546A is 2.3 V to 5.5 V applied at the VCC pin. When the PCA9546A is powered on for the first time or anytime the device must be reset by cycling the power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly. 10.
PAGE 20
PCA9546A SCPS148G – OCTOBER 2005 – REVISED MAY 2016 www.ti.com 11.2 Layout Example LEGEND Partial Power Plane VIA to Power Plane Polygonal Copper Pour To I2C Master VIA to GND Plane (Inner Layer) VDPUM By-pass/De-coupling capacitors GND VCC A1 SDA RESET SCL SD0 SD1 SC1 VDPU3 A2 SC3 SD3 SC2 SD2 GND VDPU1 VDPU2 To Slave Channel 2 GND PCA9546A A0 SC0 To Slave Channel 1 VCC To Slave Channel 3 To Slave Channel 0 VDPU0 12 Device and Documentation Support 12.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE OPTION ADDENDUM www.ti.
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing PCA9546ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DGV 16 2000 330.0 12.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.8 4.0 1.6 8.0 12.0 Q1 PCA9546ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PCA9546ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9546ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 PCA9546ADR SOIC D 16 2500 333.2 345.9 28.6 PCA9546ADWR SOIC DW 16 2000 367.0 367.0 38.0 PCA9546APWR TSSOP PW 16 2000 367.0 367.0 35.0 PCA9546APWT TSSOP PW 16 250 367.0 367.0 35.0 PCA9546ARGVR VQFN RGV 16 2500 367.0 367.0 35.
PAGE 26
PAGE 27
PAGE 28
PAGE 29
PAGE 30
PAGE 31
PAGE 32
PAGE 33
PAGE 34
PAGE 35
PAGE 36
PAGE 37
PAGE 38
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.