User's Manual

Maps and Registers System Configuration Registers
124 SPARC/CPU−56T
Address: 1FF.F160.0140
16
Table 35: Timer Control Register
Bit Name Description Default Access
0 EN TIM1 Controls timer 1
0: Timer disabled
1: Timer enabled
0
2
r/w
1 EN MOD32 Switches between two 16−bit−wide timers and one
32−bit−wide timer
0: 16−bit mode enabled
1: 32−bit mode enabled
0
2
r/w
2..3 − Reserveda 00
2
r
4 EN TIM2 Controls timer 2
0: Timer disabled
1: Timer enabled
0
2
r/w
7..5
− Reserveda 000
2
r
Timer Clear Control Register
This register is used to control the status bits of both timers in the Timer Status register.
Address: 1FF.F160.0141
16
Table 36: Timer Clear Control Register
Bit
Name Description Access
0 CLR TIM1 Clears the status bits of timer 1 in the Timer Status register
0: Timer 1 status bits stay as they are.a
1: Timer 1 status bits will be cleared.
w
3..1 − Reserved w
4 CLR TIM2 Clears the status bits of timer 2 in the Timer Status register
0: Timer 2 status bits stay as they are.a
1: Timer 2 status bits will be cleared.
w
7..5
− Reserved w
Timer Status Register
The Timer Status register is used to recognize timer underrun conditions.