User's Manual

System Configuration Registers Maps and Registers
SPARC/CPU−56T 133
Bit AccessDefaultDescriptionName
5 PMC3/4 VIO This bit is set to 1 if the PMC modules 3 and 4 are
configured with a VI/O of 5V (if applicable)
0: PMC3/4 have a VI/O of 3.3V
1: PMC3/4 have a VI/O of 5V
0
2
r
6 FKBD/MSE−PRE
SENT
This bit shows which type of keyboard/mouse is
plugged into the front connector.
0: No SUN style keyboard/mouse or a PS/2 style
keyboard/mouse is plugged into the front connector.
1: A SUN style keyboard/mouse is plugged into the
front connector.
0
2
r
7
RKBD/MSE−PRE
SENT
This bit shows which type of keyboard/mouse is
plugged into the rear connector.
0: No SUN style keyboard/mouse or a PS/2 style
keyboard/mouse is plugged into the rear connector.
1: A SUN style keyboard/mouse is plugged into the
rear connector.
0
2
r
Board Configuration Status Register 2
This register gives information about additional board conditions.
a
Address: 1FF.F160.01E3
16
Table 46: Board Configuration Status Register 2
Bit
Name Description Default Access
0 PMC_EREADY This bit shows the initialization status of a non
monarch processor PMC module. PMC_EREADY is a
wired OR signal of all PMC modules.
0: At least one of the PMC modules has not
completed its initialization cycle.
1: All PMC modules have completed their
initialization and are able to respond to configuration
cycles from the host processor.
1
2
r
7..1 − Reserved 0000000
2
r
Hardware Revision Register
The Hardware Revision register is used to identify current PCB and FPGA revision.