User's Manual

Maps and Registers System Configuration Registers
132 SPARC/CPU−56T
Bit AccessDefaultSwitch Setting/FunctionalityName
5 .. 4 SW4−2 and SW4−1 VME Slot 1 Detection
00
2
: SW4−2 ON and SW4−1 ON (VME slot 1
function)
10
2
: SW4−2 OFF and SW4−1 ON (VME slot 1
function )
01
2
: SW4−1 OFF (Automatic VMEbus slot 1
detection enabled)
11
2
r
6 SW4−3 External VMEbus SYSRESET function
0: ON (VMEbus SYSRESET does not generate
board reset)
1: OFF (VMEbus SYSRESET generates board
reset)
1
2
r
7
SW4−4 VMEbus SYSRESET generation
0: ON (board reset is not driven to VMEbus
SYSRESET)
1: OFF (board reset is driven to VMEbus
SYSRESET)
1
2
r
Board Configuration Status Register 1
This register reflects the hardware configuration of the CPU board.
a
Address: 1FF.F160.01E2
16
Table 45: Board Configuration Status Register 1
Bit
Name Description Default Access
1..0 IO−PRESENT These bits show whether an I/O board is plugged on
the CPU board (if applicable).a
0: No I/O board present
1: I/O board present
2: Reserved
3: Reserved
00
2
r
3..2 IOBP−PRESENT These bits are showing which type of the IOBP−CPU
is plugged at the rear side of the CPU board.
0: No IOBP−CPU present
1: IOBP−CPU/3 present
2: IOBP−CPU/5 present
3: Reserved
00
2
r
4
PMC1/2 VIO This bit is set to 1 if the PMC modules 1 and 2 are
configured with a VI/O of 5V (if applicable)
0: PMC1/2 have a VI/O of 3.3V
1: PMC1/2 have a VI/O of 5V
0
2
r