User's Manual

System Configuration Registers Maps and Registers
SPARC/CPU−56T 125
Address: 1FF.F160.0144
16
Table 37: Timer Status Register
Bit Name Description Default Access
0 STAT TIM1 Indicates an underrun of timer 1. This can only occur if
timer 1 is enabled and the initial value is greater than 0.a
0: No underrun of timer 1 has occurred.
1: An underrun of timer 1 has occurred.
0
2
r
1 ERR TIM1 Indicates that more than one timer underruns without
clearance have occurred. It is a status for a missed timer
underrun and can only occur if timer 1 is enabled and the
initial value is greater than 0.
0: No more than one timer underruns of timer 1 have
occurred.
1: More than one timer underruns of timer 1 have
occurred.
0
2
r
2..3 − Reserved 00
2
r
4 STAT TIM2 Indicates an underrun of timer 2. This can only occur if
timer 2 is enabled, the initial value is greater than 0 and if
the 16−bit mode is enabled.
0: No underrun of timer 2 has occurred.
1: An underrun of timer 2 has occurred.
0
2
r
5 ERR TIM2 Indicates that more than one timer underruns without
clearance have occurred. It is a status for a missed timer
underrun and can only occur, if timer 2 is enabled, the
initial value is greater than 0 and if the 16−bit mode is
enabled.
0: No more than one timer underruns of timer 2 have
occurred.
1: More than one time underrun of timer 2 has occurred.
0
2
r
6..7
Reserved Reserved 00
2
r
Timer Initial Control Registers
The following four registers are used to set up the run−out time of both timers. The 32 bits
are distributed as big endian, which means the first register (1FF.F160.0148) represents the
bits 31..24 and so on.