Integration Manual

GTM353W Integration Manual
Author:
R
. Claessens
Version:
4.0 Draft 2
Creation Date:
September 20, 2006
Page:
29 of 52
Option Confidential:
This document is Option Confidential - it may not be duplicated, neither distributed externally without prior and written permission of
Option NV.
· Figure 16 PCM_SYNC timing
· Figure 17 PCM_UPLINK, Codec to Module timing
· Figure 18 PCM_DOWNLINK, Module to Codec timing
Parameter Description Min Typical Max Units
t(sync)
PCM_SYNC cycle time
-- 125 -- µs
t(synca)
PCM_SYNC asserted time
62.4 62.5 -- µs
t(syncd)
PCM_SYNC deasserted time
62.4 62.5 -- µs
t(clk)
PCM_CLK cycle time
-- 7.8 -- µs
t(clkh)
PCM_CLK high time
3.8 3.9 -- µs
t(clkl)
PCM_CLK low time
3.8 3.9 -- µs
t(susync)
PCM_SYNC setup time to PCM_CLK rising
ns
t(hsync)
PCM_SYNC hold time after PCM_CLK rising
ns
t(sudin)
PCM_UPLINK setup time to PCM_CLK falling
ns
t(hdin)
PCM_UPLINK hold time after PCM_CLK falling
ns
t(pdout)
Delay from PCM_CLK rising to PCM_DOWNLINK
valid
ns
t(zdout
Delay from PCM_CLK falling to PCM_DOWNLINK
HIGH-Z
ns
· Table 17 PCM Codec timing parameters