Datasheet

Functional overview STM32H743xI
24/231 DS12110 Rev 5
3.7 Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1 Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
 Internal oscillators:
–
64 MHz HSI clock
– 48 MHz RC oscillator
– 4 MHz CSI clock
– 32 kHz LSI clock
 External oscillators:
– 4-48 MHz HSE clock
– 32.768 kHz LSE clock
The RCC provides three PLLs: one for system clock,
two for kernel clocks.
The system starts on the HSI clock. The u
ser application can then select the clock
configuration.
3.7.2 System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the
following cases:
 Power
-on reset (pwr_por_rst)
 Brownout reset
 Low level on NRST pin (external reset)
 Window watchdog
 Independent watchdog
 Software reset
 Low-power mode security reset
 Exit from Standby