Datasheet

DS12110 Rev 5 189/231
STM32H743xI Electrical characteristics
199
SAI characteristics
Unless otherwise specified, the parameters given in Table 105 for SAI are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions, with the following
configuration:
 Output speed
is set to OSPEEDRy[1:0] = 10
 Capacitive load C=30 pF
 Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 105. SAI characteristics
(1)
Symbol Parameter Conditions Min Max Unit
f
MCK
SAI Main clock output - 256 x 8K 256xFs MHz
F
CK
SAI clock frequency
(2)
Master data: 32 bits - 128xFs
(3)
MHz
Slave data: 32 bits - 128xFs
t
v(FS)
FS valid time
Master mode
2.7VDD3.6V
-15
ns
Master mode
1.71VDD3.6V
-20
t
su(FS)
FS setup time Slave mode 7 -
t
h(FS)
FS hold time
Master mode 1 -
Slave mode 1 -
t
su(SD_A_MR)
Data input setup time
Master receiver 0.5 -
t
su(SD_B_SR)
Slave receiver 1 -
t
h(SD_A_MR)
Data input hold time
Master receiver 3.5 -
t
h(SD_B_SR)
Slave receiver 2 -
t
v(SD_B_ST)
Data output valid time
Slave transmitter (after enable edge)
2.7V
DD
3.6V
-17
ns
Slave transmitter (after enable edge)
1.62V
DD
3.6V
-20
t
h(SD_B_ST)
Data output hold time Slave transmitter (after enable edge) 7 -
t
v(SD_A_MT)
Data output valid time
Master transmitter (after enable edge)
2.7V
DD
3.6V
-17
Master transmitter (after enable edge)
1.62V
DD
3.6V
-20
t
h(SD_A_MT)
Data output hold time Master transmitter (after enable edge) 7.55 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With F
S
=192 kHz.