Datasheet

Electrical characteristics STM32H743xI
176/231 DS12110 Rev 5
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 97 for DFSDM are derived from
tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage
summarized in Table 23: General operating conditions, with the following configuration:
 Output speed
is set to OSPEEDRy[1:0] = 10
 Capacitive load C = 30 pF
 Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DA
TINx, DFSDMx_CKOUT for
DFSDMx).
Table 97. DFSDM measured timing 1.62-3.6 V
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
DFSDMCLK
DFSDM clock 1.62 V < V
DD
< 3.6 V - - f
SYSCLK
MHz
f
CKIN
(1/T
CKIN
)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 V < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
0),
1.62 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]0),
2.7 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
f
CKOUT
Output clock
frequency
1.62 < V
DD
< 3.6 V - - 20
DuCy
CKOUT
Output clock
frequency duty
cycle
1.62 < V
DD
< 3.6 V 45 50 55 %