Datasheet

DS12110 Rev 5 159/231
STM32H743xI Electrical characteristics
199
Figure 37. Quad-SPI timing diagram - SDR mode
Figure 38. Quad-SPI timing diagram - DDR mode
Table 83. Quad SPI characteristics in DDR mode
(1)
Symbol Parameter Conditions Min Typ Max Unit
F
ck1/t(CK)
Quad-SPI clock
frequency
2.7 V<V
DD
<3.6 V
CL=20 pF
--100
MHz
1.62 V<V
DD
<3.6 V
CL=15 pF
--100
t
w(CKH)
Quad-SPI clock high and
low time
-
t
(CK)
/2 - 0.5 - t
(CK)
/2
ns
t
w(CKL)
t
(CK)
/2 - t
(CK)
/2+0.5
t
sr(IN)
, t
sf(IN)
Data input setup time - 2 - -
t
hr(IN)
, t
hf(IN)
Data input hold time - 2 - -
t
vr(OUT)
,
t
vf(OUT)
Data output valid time
DHHC=0 - 3.5 4
DHHC=1
Pres=1, 2...
-t
(CK)
/4+3.5 t
(CK)
/4+4
t
hr(OUT)
,
t
hf(OUT)
Data output hold time
DHHC=0 3 - -
DHHC=1
Pres=1, 2...
t
(CK)
/4+3 - -
1. Guaranteed by characterization results.
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