Datasheet

DS12110 Rev 5 157/231
STM32H743xI Electrical characteristics
199
Table 80. SDRAM write timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
fmc_ker_ck
− 12T
fmc_ker_ck
+ 0.5
ns
t
d(SDCLKL _Data
) Data output valid time - 3
t
h(SDCLKL _Data)
Data output hold time 0 -
t
d(SDCLKL_Add)
Address valid time - 1.5
t
d(SDCLKL_SDNWE)
SDNWE valid time - 1.5
t
h(SDCLKL_SDNWE)
SDNWE hold time 0.5 -
t
d(SDCLKL_ SDNE)
Chip select valid time - 1.5
t
h(SDCLKL-_SDNE)
Chip select hold time 0.5 -
t
d(SDCLKL_SDNRAS)
SDNRAS valid time - 1
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0.5 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 1
t
d(SDCLKL_SDNCAS)
SDNCAS hold time 0.5 -
Table 81. LPSDR SDRAM write timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
fmc_ker_ck
− 12T
fmc_ker_ck
+ 0.5
ns
t
d(SDCLKL _Data
) Data output valid time - 2.5
t
h(SDCLKL _Data)
Data output hold time 0 -
t
d(SDCLKL_Add)
Address valid time - 2.5
t
d(SDCLKL-SDNWE)
SDNWE valid time - 2.5
t
h(SDCLKL-SDNWE)
SDNWE hold time 0 -
t
d(SDCLKL- SDNE)
Chip select valid time - 3
t
h(SDCLKL- SDNE)
Chip select hold time 0 -
t
d(SDCLKL-SDNRAS)
SDNRAS valid time - 1.5
t
h(SDCLKL-SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL-SDNCAS)
SDNCAS valid time - 1.5
t
d(SDCLKL-SDNCAS)
SDNCAS hold time 0 -