Datasheet

Electrical characteristics STM32H743xI
156/231 DS12110 Rev 5
Figure 36. SDRAM write access waveforms
Table 79. LPSDR SDRAM read timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
W(SDCLK)
FMC_SDCLK period 2T
fmc_ker_ck
− 12T
fmc_ker_ck
+ 0.5
ns
t
su(SDCLKH_Data)
Data input setup time 2 -
t
h(SDCLKH_Data)
Data input hold time 1.5 -
t
d(SDCLKL_Add)
Address valid time - 2.5
t
d(SDCLKL_SDNE)
Chip select valid time - 2.5
t
h(SDCLKL_SDNE)
Chip select hold time 0 -
t
d(SDCLKL_SDNRAS
SDNRAS valid time - 0.5
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 1.5
t
h(SDCLKL_SDNCAS)
SDNCAS hold time 0 -
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