Datasheet

DS12110 Rev 5 155/231
STM32H743xI Electrical characteristics
199
SDRAM waveforms and timings
In all timing tables, the T
fmc_ker_ck
is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
 For
1.8 V<V
DD
<3.6V: FMC_CLK =100 MHz at 20 pF
 For 1.62 V<
DD
<1.8 V, FMC_CLK =100 MHz at 30 pF
Figure 35. SDRAM read access waveforms (CL = 1)
Table 78. SDRAM read timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
fmc_ker_ck
− 12T
fmc_ker_ck
+ 0.5
ns
t
su(SDCLKH _Data)
Data input setup time 2 -
t
h(SDCLKH_Data)
Data input hold time 1 -
t
d(SDCLKL_Add)
Address valid time - 1.5
t
d(SDCLKL- SDNE)
Chip select valid time - 1.5
t
h(SDCLKL_SDNE)
Chip select hold time 0.5 -
t
d(SDCLKL_SDNRAS)
SDNRAS valid time - 1
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0.5 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 0.5
t
h(SDCLKL_SDNCAS)
SDNCAS hold time 0 -
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