Datasheet

DS12110 Rev 5 149/231
STM32H743xI Electrical characteristics
199
Table 73. Synchronous multiplexed PSRAM write timings
(1)
Symbol Parameter Min Max Unit
t
w(CLK)
FMC_CLK period 2T
fmc_ker_ck
− 1 -
ns
t
d(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 1
t
d(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
fmc_ker_ck
+ 0.5 -
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 1.5
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 -
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 2
t
d(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25) T
fmc_ker_ck
-
t
d(CLKL-NWEL)
FMC_CLK low to FMC_NWE low - 1.5
t
(CLKH-NWEH)
FMC_CLK high to FMC_NWE high T
fmc_ker_ck
+ 0.5 -
t
d(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid - 2.5
t
d(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid 0 -
t
d(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low - 2.5
t
d(CLKL-NBLL)
FMC_CLK low to FMC_NBL low - 2
t
d(CLKH-NBLH)
FMC_CLK high to FMC_NBL high T
fmc_ker_ck
+ 0.5 -
t
su(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 2 -
t
h(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.