Datasheet

Electrical characteristics STM32H743xI
140/231 DS12110 Rev 5
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)
Symbol Parameter Min Max Unit
t
w(NE)
FMC_NE low time 2T
fmc_ker_ck
 12 T
fmc_ker_ck
+1
ns
t
v(NOE_NE)
FMC_NEx low to FMC_NOE low 0 0.5
t
w(NOE)
FMC_NOE low time 2T
fmc_ker_ck
 12T
fmc_ker_ck
+ 1
t
h(NE_NOE)
FMC_NOE high to FMC_NE high hold time 0 -
t
v(A_NE)
FMC_NEx low to FMC_A valid - 0.5
t
h(A_NOE)
Address hold time after FMC_NOE high 0 -
t
v(BL_NE)
FMC_NEx low to FMC_BL valid - 0.5
t
h(BL_NOE)
FMC_BL hold time after FMC_NOE high 0 -
t
su(Data_NE)
Data to FMC_NEx high setup time 11 -
t
su(Data_NOE)
Data to FMC_NOEx high setup time 11 -
t
h(Data_NOE)
Data hold time after FMC_NOE high 0 -
t
h(Data_NE)
Data hold time after FMC_NEx high 0 -
t
v(NADV_NE)
FMC_NEx low to FMC_NADV low - 0
t
w(NADV)
FMC_NADV low time - T
fmc_ker_ck
+ 1
1. Guaranteed by characterization results.
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
FMC_NE low time 7T
fmc_ker_ck
+1 7T
fmc_ker_ck
+1
ns
t
w(NOE)
FMC_NWE low time 5T
fmc_ker_ck
15T
fmc_ker_ck
+1
t
w(NWAIT)
FMC_NWAIT low time T
fmc_ker_ck
0.5
t
su(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high 4T
fmc_ker_ck
+11 -
t
h(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid 3T
fmc_ker_ck
+11.5 -
1. Guaranteed by characterization results.
2. N
WAIT
pulse width is equal to 1 AHB cycle.