STM32H743xI 32-bit Arm® Cortex®-M7 400MHz MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces Datasheet - production data Features )%*$ Core 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.
STM32H743xI 4 DMA controllers to unload the CPU 2× operational amplifiers (8 MHz bandwidth) 1× high-speed master direct memory access controller (MDMA) with linked list support 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters 2× dual-port DMAs with FIFO 1× basic DMA with request router capabilities Up to 35 communication peripherals Graphics LCD-TFT controller up to XGA resolution Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load 4× I2
STM32H743xI Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Memory protection unit (MPU) . . . .
Contents 4 4/231 STM32H743xI 3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 32 3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . .
STM32H743xI Contents 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . .
Contents 7 STM32H743xI 6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.27 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 176 6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . .
STM32H743xI List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . .
List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93.
STM32H743xI Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. List of tables DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures STM32H743xI List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
STM32H743xI Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. List of figures SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . .
Introduction 1 STM32H743xI Introduction This document provides information on STM32H743xI microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering information. This document should be read in conjunction with the STM32H743xI reference manual (RM0433), available from the STMicroelectronics website www.st.com.
STM32H743xI 2 Description Description STM32H743xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 400 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H743xI devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
Description STM32H743xI STM32H743xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.
STM32H743xI Description Table 2.
Description STM32H743xI Table 2. STM32H743xI features and peripheral counts (continued) Peripherals STM32H 743VI STM32H 743AI STM32H 743II STM32H 743BI STM32H 743XI Ambient temperatures: –40 up to +85 °C(4) Operating temperatures Package STM32H 743ZI Junction temperature: –40 to + 125 °C LQFP100 TFBGA100(5) LQFP144 UFBGA 169(5) LQFP176 UFBGA 176+25 LQFP208 TFBGA 240+25 1.
STM32H743xI Description Figure 1. STM32H743xI block diagram 0,, 50,, 7R $3% SHULSKHUDOV 0',2 DV $) '3 '0 673 6'00&B 1;7 8/3, &. '3 '0 ,' '> @ 9%86 '> @ ',5 &0' &. DV $) ,' 9%86 $+% 0+] ' 7&0 .% ' 7&0 .% '0$ $;,0 0% )/$6+ ' &DFKH .% /&' 7)7 ::'* -3(* 6' 6&. )6 0&/. '> @ &.
Functional overview STM32H743xI 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.
STM32H743xI Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H743xI devices embed up to 2 Mbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: One Flash word (8 words, 32 bytes or 256 bits) 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: 3.3.
Functional overview STM32H743xI Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: 7 ECC bits are added per 32-bit word.
STM32H743xI Functional overview The VCORE domain is split into the following power domains that can be independently switch off. – D1 domain containing some peripherals and the Cortex®-M7 core. – D2 domain containing a large part of the peripherals. – D3 domain containing some peripherals and the system control.
Functional overview 3.5.2 STM32H743xI Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in Reset mode when VDD is below this threshold, Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold.
STM32H743xI 3.6 Functional overview Low-power strategy There are several ways to reduce power consumption on STM32H743xI: Decrease dynamic power consumption by slowing down the system clocks even in Run mode and individually clock gating the peripherals that are not used. Save power consumption when the CPU is idle, by selecting among the available lowpower mode according to the user application needs.
Functional overview 3.7 STM32H743xI Reset and clock controller (RCC) The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption.
STM32H743xI 3.8 Functional overview General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.
Functional overview 26/231 Figure 3. STM32H743xI bus matrix $+%6 &38 ,7&0 .E\WH 0'0$ '0$ ' '0$ B0(0 6'00& /7'& ' WR ' $+% '0$ '0$ B0(0 '0$ (WKHUQHW 6'00& 86%+6 0$& 86%+6 '0$ B3(5,3+ '7&0 .E\WH $+%3 $;,0 , ' .% .% '0$ B3(5,3+ &RUWH[ 0 $3% 65$0 .E\WH $+% 65$0 .E\WH 65$0 .E\WH )ODVK $ 0E\WH DS12110 Rev 5 $+% )ODVK % 0E\WH $+% $;, 65$0 .E\WH $3% 463, $3% )0& ELW $;, EXV PDWUL[ ' GRPDLQ ELW $+% EXV PDWUL[ ' GRPDLQ ' W
STM32H743xI 3.10 Functional overview DMA controllers . The devices feature four DMA instances to unload CPU activity: A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex®-M7 TCM memories. The MDMA is located in D1 domain.
Functional overview 3.12 STM32H743xI Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core.
STM32H743xI 3.15 Functional overview Flexible memory controller (FMC) The FMC controller main features are the following: Interface with static-memory mapped devices including: – 3.
Functional overview STM32H743xI In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer. 3.
STM32H743xI 3.20 Functional overview Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
Functional overview STM32H743xI The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 3.
STM32H743xI Functional overview short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..
Functional overview 3.25 STM32H743xI LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.
STM32H743xI Functional overview All timer counters can be frozen in Debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5.
Functional overview STM32H743xI Table 5. Timer feature comparison (continued) Timer type Timer DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Complementary output Max interface clock (MHz) Max timer clock (MHz) (1) Yes 0 No 100 200 No 0 No 100 200 1.
STM32H743xI 3.28.2 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
Functional overview 3.28.4 STM32H743xI Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
STM32H743xI 3.29 Functional overview Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. Two programmable alarms. On-the-fly correction from 1 to 32767 RTC clock pulses.
Functional overview 3.30 STM32H743xI Inter-integrated circuit interface (I2C) STM32H743xI devices embed four I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: 3.31 I2C-bus specification and user manual rev.
STM32H743xI Functional overview All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: Start bit detection Any received data frame A specific programmed data frame Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 6.
Functional overview STM32H743xI The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: Start bit detection Any received data frame A specific programmed data frame Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud.
STM32H743xI 3.35 Functional overview SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: Up to 4 inputs available Automatic symbol rate detection Maximum symbol rate: 12.
Functional overview 3.37 STM32H743xI Management Data Input/Output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers Configurable slave (port) address Independently maskable interrupts/events: 3.
STM32H743xI 3.40 Functional overview Universal serial bus on-the-go high-speed (OTG_HS) The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both integrate the transceivers for full-speed operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s).
Functional overview STM32H743xI The devices include the following features: 3.
STM32H743xI 4 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals.
Pin descriptions 5 STM32H743xI Pin descriptions 3$ 3$ 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3% %227 3% 3% 3( 3( 966 9'' Figure 4.
STM32H743xI Pin descriptions Figure 5.
Pin descriptions STM32H743xI SLQV 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9'' 86% 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3
STM32H743xI Pin descriptions Figure 7.
Pin descriptions STM32H743xI PINOUT UNDER DEVELOPMENT SLQV
STM32H743xI Pin descriptions Figure 9.
Pin descriptions STM32H743xI SLQV
STM32H743xI Pin descriptions Figure 11. TFBGA240+25 ballout 9&$3 3. 3* 3* 3' 3& 3$ 3, 3, 966 $ 966 3, 3, 3, 3% 9'' /'2 % 9%$7 966 3, 3( 3% 966 3% 3. 3* 3- 3' 3' 3& 3$ 3, 3+ 3+ 3( 3( 3% 3% 3. 3. 3* 966 3' 3& 966 3, 3$ 966 9'' /'2 3% 3% 3* 3.
Pin descriptions STM32H743xI Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions Table 8.
Pin descriptions STM32H743xI Table 8.
STM32H743xI Pin descriptions 3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use. 4. This ball should be connected to VSS. 5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch.
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/S PDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/F MC/ SDMMC2/ LCD
AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/ DFSDM PA14 JTCKSWCLK - - PA15 JTDI TIM2_CH1/ TIM2_ETR HRTIM_ FLT1 Port A Port AF1 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/S PDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/F MC/ SDMMC2/ LCD/ S
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/ CEC SPI1/2/3/4/5/ 6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/3 /6/UART7/S DMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PC14 - - - PC15 - - - Port C Port AF1 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/FM C/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/UART7 /SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD /COMP UART5/ LCD SYS SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX - - - - - - - - FMC_A10 - - EVENT -OUT - - - - - - - - - FMC_A11 - - EVENT -OUT - TIM8_BKIN - - - - - - - TIM8_BKIN_ COMP1
AF1 AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PG14 TRACED1 LPTIM1_ ETR - PG15 - - - Port G Port AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/SPDIFRX SAI2/4/TIM8/ QU
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD
Electrical characteristics 6 6.1 STM32H743xI Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
STM32H743xI 6.1.6 Electrical characteristics Power supply scheme 9'' 86% Q) Q) Figure 14. Power supply scheme 9'' 86% 9'' 86% 86% ,2V 86% UHJXODWRU 9''/'2 9&$3 /HYHO VKLIWHU ,2V 1 [ Q) [ ) ' GRPDLQ SHULSKHUDOV 5$0 ' GRPDLQ &38 SHULSKHUDOV 5$0 9'' GRPDLQ 9%$7 FKDUJLQJ +6, &6, +6, +6( 3//V %DFNXS GRPDLQ %DFNXS 9%.3 UHJXODWRU 96: 9%$7 3RZHU VZLWFK 3RZHU VZLWFK /6, /6( 57& :DNHXS ORJLF EDFNXS ,2 UHJLVWHUV ORJLF 5HVHW %.
Electrical characteristics STM32H743xI device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.
STM32H743xI Electrical characteristics Table 21.
Electrical characteristics STM32H743xI 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Operating conditions Min Max (1) 3.6 VDD Standard operating voltage - VDDLDO Supply voltage for the internal regulator VDDLDO ≤ VDD 1.62(1) 3.6 USB used 3.0 3.6 USB not used 0 3.6 ADC or COMP used 1.62 DAC used 1.8 OPAMP used 2.0 VREFBUF used 1.8 ADC, DAC, OPAMP, COMP, VREFBUF not used 0 TT_xx I/O −0.3 VDD+0.
STM32H743xI Electrical characteristics 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 6.3.2 VCAP external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 24.
Electrical characteristics 6.3.4 STM32H743xI Embedded reset and power control block characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 26.
STM32H743xI Electrical characteristics Table 26. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.
Electrical characteristics STM32H743xI Table 27. Embedded reference voltage (continued) Symbol Parameter Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. Unit % VREFINT Table 28.
STM32H743xI Electrical characteristics Table 29. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON(1) Symbol Parameter Conditions VOS1 VOS2 All peripherals disabled IDD Supply current in Run mode VOS3 VOS1 All peripherals VOS2 enabled VOS3 Max(2) frcc_c_ck (MHz) Typ TJ = 25°C TJ = 85°C TJ = 105°C TJ = 125°C 400 71 110 210 290 540 300 56 - - - - 300 50 72 170 230 370 216 37 58 150 210 380 200 35.
Electrical characteristics STM32H743xI Table 30.
STM32H743xI Electrical characteristics Table 32. Typical consumption in Run mode and corresponding performance versus code position Symbol Parameter Conditions All peripherals disabled, cache ON Supply current in Run mode IDD Code frcc_c_ck (MHz) CoreMark Typ ITCM 400 2012 71 35 FLASH A 400 2012 105 52 AXI SRAM 400 2012 105 52 SRAM1 400 2012 105 52 SRAM4 400 2012 105 ITCM 400 2012 71 FLASH A 400 593 70.5 119 AXI SRAM 400 344 70.5 205 SRAM1 400 472 74.
Electrical characteristics STM32H743xI Table 35. Typical and maximum current consumption in Stop mode, regulator ON Max(1) Symbol Parameter Flash memory in low-power mode, no IWDG D1Stop, D2Stop, D3Stop IDD(Stop) Conditions Flash memory ON, no IWDG D1Stop, D2Standby, D3Stop Flash memory OFF, no IWDG Flash memory ON, no IWDG D1Standby, D2Stop, D3Stop Flash OFF, no IWDG D1Standby, D2Standby, D3Stop Typ TJ = 25°C TJ = 85°C TJ = 105°C TJ = 125°C SVOS5 1.4 7.2(2) 49 75(2) 140 SVOS4 1.
STM32H743xI Electrical characteristics Table 37. Typical and maximum current consumption in VBAT mode Typ(1) Conditions Symbol IDD (VBAT) Parameter Supply current in standby mode Backup SRAM RTC & LSE 1.2 V OFF OFF 0.024 ON OFF 1.4 1.6 1.8 OFF ON 0.24 0.45 ON ON 1.97 2.37 Max (3 V) TJ = 25°C TJ = 85°C 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1) 24(1) 1.8 4.4(1) 22(1) 48(1) 87(1) 0.62 0.73 - - - - 2.57 2.77 - - - - 2V 3V 3.4 V TJ = TJ = 105°C 125°C Unit µA 1.
Electrical characteristics STM32H743xI The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. On-chip peripheral current consumption The MCU is placed under the following conditions: At startup, all I/O pins are in analog input configuration. All peripherals are disabled unless otherwise mentioned. The I/O compensation cell is enabled. frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode IDD(Typ) Peripheral AHB3 Unit VOS1 VOS2 VOS3 MDMA 8.3 7.6 7 DMA2D 21 20 18 JPEG 24 23 21 FLASH 9.9 9 8.3 FMC registers 0.9 0.9 0.8 FMC kernel 6.1 5.5 5.3 QUADSPI registers 1.5 1.4 1.3 QUADSPI kernel 0.9 0.8 0.7 SDMMC1 registers 8 7.2 6.8 SDMMC1 kernel 2.4 2 1.8 DTCM1 5.7 5 4.5 DTCM2 5.5 4.8 4.3 ITCM 3.2 2.9 2.6 D1SRAM1 7.6 6.8 6.1 Bridge AHB3 7.5 6.
Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral AHB2 AHB4 APB3 112/231 Unit VOS1 VOS2 VOS3 DCMI 1.7 1.7 1.7 RNG registers 1.8 1.4 1.2 RNG kernel - 9.6 9.6 SDMMC2 registers 13 12 11 SDMMC2 kernel 2.7 2.5 2.4 D2SRAM1 3.3 3.1 2.8 D2SRAM2 2.9 2.7 2.5 D2SRAM3 1.9 1.8 1.7 Bridge AHB2 0.1 0.1 0.1 GPIOA 1.1 1 0.9 GPIOB 1 0.9 0.9 GPIOC 1.4 1.3 1.3 GPIOD 1.1 1 0.9 GPIOE 1 0.
STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 Unit VOS1 VOS2 VOS3 TIM2 3.5 3.2 2.9 TIM3 3.4 3.1 2.7 TIM4 2.7 2.5 1.9 TIM5 3.2 2.9 2.5 TIM6 1 0.8 0.7 TIM7 1 0.9 0.7 TIM12 1.7 1.5 1.2 TIM13 1.5 1.3 1 TIM14 1.4 1.3 0.9 LPTIM1 registers 0.7 0.6 0.5 LPTIM1 kernel 2.3 2.1 1.9 WWDG2 0.6 0.4 0.4 SPI2 registers 1.8 1.5 1.2 SPI2 kernel 0.6 0.5 0.5 SPI3 registers 1.5 1.
Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 (continued) 114/231 Unit VOS1 VOS2 VOS3 UART5 registers 1.4 1.4 1 UART5 kernel 3.6 3.2 3.1 I2C1 registers 0.8 0.8 0.6 I2C1 kernel 2 1.8 1.7 I2C2 registers 0.7 0.7 0.4 I2C2 kernel 1.9 1.7 1.6 I2C3 registers 0.9 0.7 0.6 I2C3 kernel 2.1 1.9 1.9 HDMI-CEC registers 0.5 0.3 0.3 DAC1/2 1.4 1.1 0.9 USART7 registers 1.9 1.8 1.
STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB2 Unit VOS1 VOS2 VOS3 TIM1 5.1 4.8 4.3 TIM8 5.4 4.9 4.6 USART1 registers 2.7 2.6 2.5 USART1 kernel 0.1 0.1 0.1 USART6 registers 2.6 2.5 2.5 USART6 kernel 0.1 0.1 0.1 SPI1 registers 1.8 1.6 1.6 SPI1 kernel 1 0.8 0.6 SPI4 registers 1.6 1.5 1.5 SPI4 kernel 0.5 0.4 0.4 TIM15 3.1 2.8 2.7 TIM16 2.4 2.1 2.1 TIM17 2.2 2 1.
Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB4 Unit VOS1 VOS2 VOS3 SYSCFG 1 0.7 0.7 LPUART1 registers 1.1 1.1 1.1 LPUART1 kernel 2.6 2.4 2.1 SPI6 registers 1.6 1.5 1.4 SPI6 kernel 0.2 0.2 0.2 I2C4 registers 0.1 0.1 0.1 I2C4 kernel 2.4 2.1 2 LPTIM2 registers 0.5 0.5 0.5 LPTIM2 kernel 2.3 2.1 1.8 LPTIM3 registers 0.5 0.5 0.5 LPTIM3 kernel 2 2.1 1.5 LPTIM4 registers 0.5 0.
STM32H743xI 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 40 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: For Stop or Sleep modes: the wakeup event is WFE. WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 40.
Electrical characteristics 6.3.8 STM32H743xI External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 59: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 17. Table 41.
STM32H743xI Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 59: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 18. Table 42.
Electrical characteristics STM32H743xI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 43.
STM32H743xI Electrical characteristics Figure 19. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) %LDV FRQWUROOHG JDLQ 26&B28 7 670 DL E 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
Electrical characteristics Note: STM32H743xI For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 20. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 DL E 1.
STM32H743xI Electrical characteristics 5. Jitter measurements are performed without clock source activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 46. HSI oscillator characteristics(1) Symbol Parameter HSI frequency fHSI TRIM HSI user trimming step DuCy(HSI) Duty Cycle ΔVDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.
Electrical characteristics STM32H743xI Table 47. CSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit tstab(CSI) CSI oscillator stabilization time (to reach ±3% of fCSI) - - - 4 cycle IDD(CSI) CSI oscillator power consumption - - 23 30 µA Min Typ Max Unit VDD = 3.3 V, TJ = 25 °C (after calibration) 31.4 32 32.6 TJ = –40 to 105 °C, VDD = 1.62 to 3.6 V 29.76 - 33.60 1. Guaranteed by design. 2. Guaranteed by test in production. 3.
STM32H743xI Electrical characteristics Table 49. PLL characteristics (wide VCO frequency range)(1) (continued) Symbol tLOCK Parameter PLL lock time Cycle-to-cycle jitter Jitter Long term jitter IDD(PLL)(3) Conditions Typ Max (3) Unit (3) 150 Normal mode - 50 Sigma-delta mode (CKIN ≥ 8 MHz) - 58(3) 166(3) VCO = 192 MHz - 134 - VCO = 200 MHz - 134 - VCO = 400 MHz - 76 - VCO = 800 MHz - 39 - Normal mode - ±0.7 - Sigma-delta mode (CKIN = 16 MHz) - ±0.
Electrical characteristics STM32H743xI Table 50.
STM32H743xI Electrical characteristics Table 52. Flash memory programming (single bank configuration nDBANK=1) Symbol tprog tERASE128KB tME Min(1) Typ Max(1) Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Program/erase parallelism x 16 - 1.8 3.
Electrical characteristics 6.3.12 STM32H743xI EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
STM32H743xI Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electrical characteristics STM32H743xI Static latchup Two complementary static tests are required on six parts to assess the latchup performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 57. Electrical sensitivities Symbol LU 6.3.
STM32H743xI 6.3.15 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 59: I/O static characteristics are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Table 59. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3xVDD - - 0.4xVDD− 0.
Electrical characteristics STM32H743xI Figure 21.
STM32H743xI Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant. Table 60. Output voltage characteristics(1) Symbol Parameter Conditions(3) Min Max Unit port(2) Output low level voltage CMOS IIO=8 mA 2.7 V≤ VDD ≤3.
Electrical characteristics STM32H743xI Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V. Table 61.
STM32H743xI Electrical characteristics Table 61. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 V≤VDD≤3.6 V - 85 C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 35 - 110 C=30 pF, 1.62 V≤VDD≤2.7 V - 40 C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 166 C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 100 - 3.8 (4) (4) Fmax(2) Maximum frequency 10 C=30 pF, 2.7 V≤VDD≤3.6 V (4) (4) C=50 pF, 2.7 V≤VDD≤3.6 V (4) C=50 pF, 1.62 V≤VDD≤2.
Electrical characteristics STM32H743xI Output buffer timing characteristics (HSLV option enabled) Table 62.
STM32H743xI 6.3.16 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 59: I/O static characteristics). Unless otherwise specified, the parameters given in Table 63 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 63.
Electrical characteristics 6.3.17 STM32H743xI FMC characteristics Unless otherwise specified, the parameters given in Table 64 to Table 77 for the FMC interface are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
STM32H743xI Electrical characteristics Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms WZ 1( )0&B1( WY 12(B1( W Z 12( W K 1(B12( )0&B12( )0&B1:( WY $B1( )0&B$> @ W K $B12( $GGUHVV WY %/B1( W K %/B12( )0&B1%/> @ W K 'DWDB1( W VX 'DWDB12( WK 'DWDB12( W VX 'DWDB1( 'DWD )0&B'> @ W Y 1$'9B1( WZ 1$'9 )0&B1$'9 )0&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06 9 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Electrical characteristics STM32H743xI Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Tfmc_ker_ck − 1 2 Tfmc_ker_ck +1 0 0.5 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
STM32H743xI Electrical characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )0&B1([ )0&B12( WY 1:(B1( W K 1(B1:( WZ 1:( )0&B1:( WY $B1( )0&B$> @ WK $B1:( $GGUHVV WY %/B1( )0&B1%/> @ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )0&B'> @ W Y 1$'9B1( WZ 1$'9 )0&B1$'9 )0&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06 9 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 66.
Electrical characteristics STM32H743xI Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2) Symbol Min Max 8Tfmc_ker_ck − 1 8Tfmc_ker_ck + 1 FMC_NWE low time 6Tfmc_ker_ck − 1.5 6Tfmc_ker_ck + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 - tw(NE) tw(NWE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. 2.
STM32H743xI Electrical characteristics Table 68. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max 3Tfmc_ker_ck − 1 3Tfmc_ker_ck + 1 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5 Tfmc_ker_ck − 1 Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Tfmc_ker_ck − 0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.
Electrical characteristics STM32H743xI Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )0&B 1([ )0&B12( WY 1:(B1( W K 1(B1:( WZ 1:( )0&B1:( WK $B1:( WY $B1( )0&B $> @ $GGUHVV WY %/B1( WK %/B1:( )0&B 1%/> @ 1%/ W Y $B1( W Y 'DWDB1$'9 'DWD $GGUHVV )0&B $'> @ WK 'DWDB1:( WK $'B1$'9 W Y 1$'9B1( WZ 1$'9 )0&B1$'9 )0&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06 9 Table 70.
STM32H743xI Electrical characteristics Table 71. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Min Max 9Tfmc_ker_ck – 1 9Tfmc_ker_ck 7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5 6Tfmc_ker_ck + 3 - 4Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results.
Electrical characteristics STM32H743xI Figure 27. Synchronous multiplexed NOR/PSRAM read timings %867851 WZ &/. WZ &/. )0&B&/. 'DWD ODWHQF\ WG &/./ 1([/ )0&B1([ W G &/./ 1$'9/ WG &/.+ 1([+ WG &/./ 1$'9+ )0&B1$'9 WG &/./ $9 WG &/.+ $,9 )0&B$> @ WG &/./ 12(/ WG &/.+ 12(+ )0&B12( W G &/./ $'9 )0&B$'> @ WG &/./ $',9 WVX $'9 &/.+ $'> @ WK &/.+ $'9 WVX $'9 &/.+ ' WVX 1:$,79 &/.+ )0&B1:$,7 :$,7&)* E :$,732/ E )0&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.
STM32H743xI Electrical characteristics Table 72. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
Electrical characteristics STM32H743xI Figure 28. Synchronous multiplexed PSRAM write timings %867851 WZ &/. WZ &/. )0&B&/. 'DWD ODWHQF\ WG &/./ 1([/ WG &/.+ 1([+ )0&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )0&B1$'9 WG &/.+ $,9 WG &/./ $9 )0&B$> @ WG &/.+ 1:(+ WG &/./ 1:(/ )0&B1:( WG &/./ $',9 WG &/./ $'9 )0&B$'> @ WG &/./ 'DWD WG &/./ 'DWD $'> @ ' ' )0&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WK &/.+ 1:$,79 WG &/.
STM32H743xI Electrical characteristics Table 73. Synchronous multiplexed PSRAM write timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2Tfmc_ker_ck − 1 - - 1 Tfmc_ker_ck + 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
Electrical characteristics STM32H743xI Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings WZ &/. WZ &/. )0&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )0&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )0&B1$'9 WG &/.+ $,9 WG &/./ $9 )0&B$> @ WG &/./ 12(/ WG &/.+ 12(+ )0&B12( WVX '9 &/.+ WK &/.+ '9 WVX '9 &/.+ ' )0&B'> @ ' WVX 1:$,79 &/.+ )0&B1:$,7 :$,7&)* E :$,732/ E WK &/.+ 1:$,79 WVX 1:$,79 &/.+ )0&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WK &/.+ '9 W K &/.
STM32H743xI Electrical characteristics Figure 30. Synchronous non-multiplexed PSRAM write timings WZ &/. WZ &/. )0&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )0&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )0&B1$'9 WG &/.+ $,9 WG &/./ $9 )0&B$> @ WG &/./ 1:(/ WG &/.+ 1:(+ )0&B1:( WG &/./ 'DWD )0&B'> @ WG &/./ 'DWD ' ' )0&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WG &/.+ 1%/+ WK &/.+ 1:$,79 )0&B1%/ 06 9 Table 75.
Electrical characteristics STM32H743xI NAND controller waveforms and timings Figure 31 through Figure 34 represent synchronous waveforms, and Table 76 and Table 77 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: COM.FMC_SetupTime = 0x01 COM.FMC_WaitSetupTime = 0x03 COM.FMC_HoldSetupTime = 0x02 COM.FMC_HiZSetupTime = 0x01 ATT.FMC_SetupTime = 0x01 ATT.FMC_WaitSetupTime = 0x03 ATT.
STM32H743xI Electrical characteristics Figure 32. NAND controller waveforms for write access )0&B1&([ $/( )0&B$ &/( )0&B$ WK 1:( $/( WG $/( 1:( )0&B1:( )0&B12( 15( WK 1:( ' WY 1:( ' )0&B'> @ 06 9 Figure 33.
Electrical characteristics STM32H743xI Figure 34. NAND controller waveforms for common memory write access )0&B1&([ $/( )0&B$ &/( )0&B$ WG $/( 12( WZ 1:( WK 12( $/( )0&B1:( )0&B1 2( WG ' 1:( WY 1:( ' WK 1:( ' )0&B'> @ 06 9 Table 76. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4Tfmc_ker_ck − 0.5 4Tfmc_ker_ck + 0.
STM32H743xI Electrical characteristics SDRAM waveforms and timings In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: For 1.8 V @ 5RZ Q &RO &RO &ROL &ROQ WK 6'&/./B$GG& WK 6'&/./B61'( WG 6'&/./B61'( )0&B6'1(> @ WK 6'&/.
Electrical characteristics STM32H743xI Table 79. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.
STM32H743xI Electrical characteristics Table 80. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.
Electrical characteristics 6.3.18 STM32H743xI Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 82 and Table 83 for Quad-SPI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Measurement points are done at CMOS levels: 0.
STM32H743xI Electrical characteristics Table 83. Quad SPI characteristics in DDR mode(1) Symbol Fck1/t(CK) tw(CKH) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 V
Electrical characteristics 6.3.19 STM32H743xI Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 85 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions. Table 84.
STM32H743xI Electrical characteristics Table 85. ADC characteristics(1) (continued) Symbol Conditions Min Typ Max Unit fADC = 36 MHz - - 3.
Electrical characteristics STM32H743xI Table 86.
STM32H743xI Electrical characteristics being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. Figure 39.
Electrical characteristics STM32H743xI Figure 40. Typical connection diagram using the ADC 670 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/ $ ELW FRQYHUWHU & $'& DL E 1. Refer to Table 85 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
STM32H743xI Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 95() ) Q) 9''$ ) Q) 966$ 95() 06Y 9 1.
Electrical characteristics 6.3.21 STM32H743xI DAC electrical characteristics Table 87. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.
STM32H743xI Electrical characteristics Table 87.
Electrical characteristics STM32H743xI Table 88. DAC accuracy(1) (continued) Symbol Parameter OffsetCal Offset error at code 0x800 after factory calibration Gain Gain Conditions error(5) DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ VREF+ = 3.6 V Min Typ Max - - ±5 Unit LSB VREF+ = 1.
STM32H743xI 6.3.22 Electrical characteristics Voltage reference buffer characteristics Table 89. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF _OUT Voltage Reference Buffer Output Degraded mode Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.
Electrical characteristics STM32H743xI Table 89. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL=0.5 µF - - 300 - CL=1 µF - - 500 - CL=1.5 µF - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit µs mA ILOAD = 0 µA - - 15 25 ILOAD = 500 µA - - 16 30 ILOAD = 4 mA - - 32 50 µA 1. Guaranteed by design. 2.
STM32H743xI 6.3.24 Electrical characteristics VBAT monitoring characteristics Table 92. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - KΩ Q Ratio on VBAT measurement - 4 - - –10 - +10 % 9 - - µs Unit (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input 1. Guaranteed by design. Table 93. VBAT charging characteristics Symbol RBC 6.3.
Electrical characteristics 6.3.26 STM32H743xI Comparator characteristics Table 95. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 Comparator input voltage range - 0 - VDDA VBG(2) Scaler input voltage - Refer to VREFINT VSC Scaler offset voltage - - ±5 ±10 BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.
STM32H743xI 6.3.27 Electrical characteristics Operational amplifiers characteristics Table 96. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25°C, no load on output - - ±1.5 All voltages and temperature, no load - - ±2.5 - - ±3.0 - Offset trim step at low TRIMOFFSETP common input voltage TRIMLPOFFSETP (0.1*V DDA) - - 1.1 1.
Electrical characteristics STM32H743xI Table 96. OPAMP characteristics(1) (continued) Symbol VOHSAT VOLSAT tWAKEUP Parameter Conditions Min Typ Max High saturation voltage Iload=max or RLOAD=min(2), Input at VDDA VDDA −100 mV - - Low saturation voltage Iload=max or RLOAD=min(2), Input at 0 V - - 100 Normal mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.8 3.2 High speed CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.9 2.
STM32H743xI Electrical characteristics Table 96. OPAMP characteristics(1) (continued) Symbol en IDDA(OPAMP) Parameter Voltage noise density OPAMP consumption from VDDA Conditions at 1 KHz at 10 KHz Normal mode Highspeed mode output loaded with 4 kΩ no Load, quiescent mode, follower Min Typ Max - 140 - - 55 - - 570 1000 Unit nV/√ Hz µA - 610 1200 1. Guaranteed by design, unless otherwise specified. 2. RLOAD is the resistive load connected to VSSA or to VDDA. 3.
Electrical characteristics 6.3.28 STM32H743xI Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 97 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.
STM32H743xI Electrical characteristics Table 97. DFSDM measured timing 1.62-3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.
Electrical characteristics STM32H743xI ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63, WLPLQJ 63,&.6(/ 63, WLPLQJ 63,&.6(/ Figure 44. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHU WLPLQJ 6,73 6,73 UHFRYHUHG FORFN UHFRYHUHG GDWD 06 9 178/231 DS12110 Rev 5
STM32H743xI 6.3.
Electrical characteristics 6.3.
STM32H743xI Electrical characteristics Figure 46. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WK '( WY '( /&'B'( WY '$7$ /&'B5> @ /&'B*> @ /&'B%> @ 1JYFM 1JYFM 1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFN SRUFK $FWLYH ZLGWK +RUL]RQWDO EDFN SRUFK 2QH OLQH 06 9 Figure 47. LCD-TFT vertical timing diagram W&/. /&'B&/.
Electrical characteristics 6.3.31 STM32H743xI Timer characteristics The parameters given in Table 100 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 100.
STM32H743xI 6.3.32 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: Standard-mode (Sm): with a bit rate up to 100 kbit/s Fast-mode (Fm): with a bit rate up to 400 kbit/s. Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
Electrical characteristics STM32H743xI SPI interface characteristics Unless otherwise specified, the parameters given in Table 103 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.
STM32H743xI Electrical characteristics Table 103. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) Parameter Data input setup time th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 1 - - Slave mode 2 - - Master mode 2 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode, 2.7 V≤VDD≤3.6 V - 11.5 16 Slave mode 1.62 V≤VDD≤3.
Electrical characteristics STM32H743xI Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ 0,62 RXWSXW WY 62 WK 62 )LUVW ELW 287 WVX 6, WU 6&. 1H[W ELWV 287 WGLV 62 /DVW ELW 287 WK 6, )LUVW ELW ,1 026, LQSXW 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 50. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&.
STM32H743xI Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 104 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.
Electrical characteristics STM32H743xI Figure 51. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 52. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
STM32H743xI Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 105 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C=30 pF Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.
Electrical characteristics STM32H743xI Figure 53. SAI master timing waveforms I6&. 6$,B6&.B; WK )6 6$,B)6B; RXWSXW WY )6 WY 6'B07 6$,B6'B; WUDQVPLW WK 6'B07 6ORW Q 6ORW Q WVX 6'B05 WK 6'B05 6$,B6'B; UHFHLYH 6ORW Q 06 9 Figure 54. SAI slave timing waveforms I6&. 6$,B6&.B; WZ &.+B; 6$,B)6B; LQSXW WZ &./B; WK )6 WVX )6 WY 6'B67 6$,B6'B; WUDQVPLW WK 6'B67 6ORW Q WVX 6'B65 6$,B6'B; UHFHLYH 6ORW Q WK 6'B65 6ORW Q 06 9 MDIO characteristics Table 106.
STM32H743xI Electrical characteristics Figure 55.
Electrical characteristics STM32H743xI Table 107. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2) Symbol Parameter Conditions Min Typ Max 2 - - 1.5 - - - 1 2 0 - - Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD tIHD Input hold time SD fPP =25 MHz ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD tOHD Output hold default time SD fPP =25 MHz ns 1.
STM32H743xI Electrical characteristics Figure 56. SDIO high-speed mode Figure 57. SD default mode &. W29' W2+' ' &0' RXWSXW DL Figure 58. DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 CAN (controller area network) interface Refer to Section 6.3.
Electrical characteristics STM32H743xI USB OTG_FS characteristics The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 109. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit USB transceiver operating voltage - 3.0(1) - 3.
STM32H743xI Electrical characteristics Figure 59.
Electrical characteristics STM32H743xI Figure 60. Ethernet SMI timing diagram W0'& (7+B0'& WG 0',2 (7+B0',2 2 WVX 0',2 WK 0',2 (7+B0',2 , 06 9 Table 112 gives the list of Ethernet MAC signals for the RMII and Figure 61 shows the corresponding timing diagram. Table 112. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(CRS) Carrier sense setup time 2.
STM32H743xI Electrical characteristics Table 113. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 4.5 6.5 11 td(TXD) Transmit data valid delay time 7 7.5 15 Unit ns 1.
Electrical characteristics STM32H743xI Table 114. Dynamics characteristics: JTAG characteristics(1) Symbol Parameter Fpp 1/tc(TCK) TCK clock frequency Conditions Min Typ Max 2.7 V
STM32H743xI Electrical characteristics Figure 63. JTAG timing diagram WF 7&. 7&. WVX 706 7', WK 706 7', WZ 7&./ WZ 7&.+ 7', 706 WRY 7'2 WRK 7'2 7'2 06Y 9 Figure 64. SWD timing diagram WF 6:&/. 6:&/. WVX 6:',2 WK 6:',2 WZ6:&/./ WZ 6:&/.
Package information 7 STM32H743xI Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 65.
STM32H743xI Package information Table 116. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.
Package information STM32H743xI Figure 66. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint DL F 1. Dimensions are expressed in millimeters.
STM32H743xI Package information Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 67. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ (6 + 9,7 5 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
Package information 7.2 STM32H743xI TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 68. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $ EDOO LQGH[ $ EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) ( ( * $ % & ' ( ) * + . H $ %27720 9,(: E %$//6 HHH & $ % III & 723 9,(: $ 4B0(B9 1. Drawing is not to scale. Table 117. TFBGA100, 8 x 8 × 0.
STM32H743xI Package information Table 117. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.
Package information STM32H743xI Device marking for TFBGA100 Table 118. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm The following figure gives an example of topside marking versus pin 1 position identifier location.
STM32H743xI LQFP144 package information Figure 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ & $ PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E 7.3 Package information ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale.
Package information STM32H743xI Table 119. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
STM32H743xI Package information Figure 72. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters.
Package information STM32H743xI Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 73. LQFP144 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 (6 + =,7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
STM32H743xI 7.4 Package information UFBGA169 package information Figure 74. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH $ $ GGG = $ $ $ E 6,'( 9,(: $ EDOO LGHQWLILHU $ EDOO LQGH[ DUHD ; ( ( H ) $ ) ' ' H < 1 %27720 9,(: 723 9,(: E EDOOV HHH 0 = ; < III 0 = $ <9B0(B9 1. Drawing is not in scale. Table 120. UFBGA169 - 169-pin, 7 x 7 mm, 0.
Package information STM32H743xI Table 120. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 7.5 LQFP176 package information Figure 75.
STM32H743xI Package information Table 121. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.
Package information STM32H743xI Figure 76. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint 7B)3B9 1. Dimensions are expressed in millimeters.
STM32H743xI Package information Device marking for LQFP176 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 77. LQFP176 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ (6 + ,,7 5HYLVLRQ FRGH < :: 'DWH FRGH 5 3LQ LGHQWLILHU 06Y 9 1.
Package information 7.6 STM32H743xI LQFP208 package information Figure 78. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*( 3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale.
STM32H743xI Package information Table 122. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1811 1.1732 1.1890 D1 27.800 28.000 28.200 1.1024 1.0945 1.1102 D3 - 25.500 - - 1.
Package information STM32H743xI Figure 79. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 8+B)3B9 1. Dimensions are expressed in millimeters.
STM32H743xI Package information Device marking for LQFP208 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 80. LQFP208 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ (6 + %,7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1.
Package information 7.7 STM32H743xI UFBGA176+25 package information Figure 81. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ ϰ ĚĚĚ ϯ $ ϭ ď Ğ $ EDOO LGHQWLILHU ( $ EDOO LQGH[ DUHD $ ' Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & $ ( B0(B9 1. Drawing is not to scale. Table 123. UFBGA176+25 - ball, 10 x 10 mm, 0.
STM32H743xI Package information Table 123. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.
Package information STM32H743xI Device marking for UFBGA176+25 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 83. UFBGA176+25 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ (6 + ,, 'DWH FRGH %DOO $ LGHQWLILHU < :: 06Y 9 1.
STM32H743xI TFBGA240+25 package information GGG & Figure 84. TFBGA - 240+25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package outline 6($7,1* 3/$1( $ $ & $ $ EDOO LGHQWLILHU ' ' H ( * $ ( 7.8 Package information H 6 ) %27720 9,(: E EDOOV 723 9,(: $ 8B0(B9 1. Dimensions are expressed in millimeters.
Package information STM32H743xI Table 125. TFBG - 240 +25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 13.850 14.000 14.150 0.5453 0.5512 0.5571 D1 - 12.800 - - 0.5039 - E 13.850 14.000 14.150 0.5453 0.5512 0.5571 E1 - 12.800 - - 0.5039 - e - 0.
STM32H743xI Package information Table 126. TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch) Dimension Recommended values Pitch 0.8 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for TFBGA240+25 The following figure gives an example of topside marking versus pin 1 position identifier location.
Package information 7.9 STM32H743xI Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts.
STM32H743xI 8 Ordering information Ordering information Table 128. STM32H743xI ordering information scheme Example: STM32 H 743 V I T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 743 = STM32H7x3 line Pin count V = 100 pins Z = 144 pins A = 169 pins I = 176 pins/balls B = 208 pins X = 240 balls Flash memory size I = 2 Mbytes Package T = LQFP K = UFBGA pitch 0.65 mm I = UFBGA pitch 0.
Revision history 9 STM32H743xI Revision history Table 129. Document revision history Date Revision 22-Jun-2017 1 Initial release. 2 Updated list of features. Changed datasheet status to “production data”. Added UFBGA169 and TFBGA100 packages and well as notes related their status on cover page and in Table 2: STM32H743xI features and peripheral counts. Differentiated number of GPIOs for each package in Table 2: STM32H743xI features and peripheral counts.
STM32H743xI Revision history Table 129. Document revision history Date 23-Oct-2017 18-May-2018 Revision Changes 3 Features: – Removed secure firmware upgrade support. – Total current consumption changed to 4 µA minimum. Updated Figure 7: UFBGA169 ballout. Updated dpad and dsm in Table 126: TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch). 4 Updated LSI clock frequency and ADC on cover page. Removed note related to UFBGA169 package.
Revision history STM32H743xI Table 129. Document revision history Date 18-May-2018 13-Jul-2018 230/231 Revision Changes 4 (continued) Updated typical and maximum current consumption in Table 36: Typical and maximum current consumption in Standby mode and Table 37: Typical and maximum current consumption in VBAT mode. Added note to fLSI in Table 48: LSI oscillator characteristics. Updated Figure 21: VIL/VIH for all I/Os except BOOT0.
STM32H743xI IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.