Data Sheet

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mni
TM
ision
DESCRIPTION OF CHANGES (CONTINUED)
In Table 6 on page 14, changed description of register 0x16 from “Reserved” to:
Register 16
Bit[7]: Bit shift test pattern options
Bit[6:0]: Reserved
In Table 6 on page 14, changed description of register 0x17 from “Horizontal Sensor Size”
to “Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4])”
In Table 6 on page 14, changed description of register 0x18 from “Horizontal Frame
(HREF column) end high 8-bit (low 2 bits are at HREF[1:0])” to “Horizontal Sensor Size
(2 LSBs are at HREF[1:0])”
In Table 6 on page 14, changed description of register 0x19 from “Vertical Frame (row)
start high 8-bit (low 1 bit is at HREF[6])” to “Vertical Frame (row) Start 8 MSBs (1 LSB
is at HREF[6])”
In Table 6 on page 14, changed description of register 0x1A from “Vertical Sensor Size”
to “Vertical Sensor Size (1 LSB is at HREF[2])”
In Table 6 on page 15, changed default value of register COM11 (0x20) from “04” to “10”
In Table 6 on page 15, changed name, default value, and R/W of register 0x28 from
“RSVD”, “XX”, and “–” to “REG28”, “00”, and “RW”, respectively
In Table 6 on page 15, changed description of register 0x28 from “Reserved” to:
Register 28
Bit[7:1]: Reserved
Bit[0]: Selection on the number of dummy rows, N
In Table 6 on page 16, changed default value of register HREF (0x32) from “80” to “00”
In Table 6 on page 16, changed description of register DM_LNL (0x33) from “Dummy
Line Low 8 Bits” to “Dummy Row Low 8 Bits”
In Table 6 on page 16, changed description of register DM_LNH (0x34) from “Dummy
Line High 8 Bits” to “Dummy Row High 8 Bits”
In Table 6 on page 16, changed default value of register COM13 (0x3E) from “F3” to
“E2”
In Table 6 on page 16, changed description of register COM13 (0x3E) from:
Common Control 13
Bit[7]: Analog processing channel BLC ON/OFF control
Bit[6]: ADC channel BLC ON/OFF control
Bit[5:0]: Reserved
to:
Common Control 13
Bit[7]: BLC enable
Bit[6]: ADC channel BLC ON/OFF control
Bit[5]: Analog processing channel BLC ON/OFF control
Bit[4:3]: Reserved
Bit[2]: ABLC gain trigger enable
Bit[1:0]: Reserved