User Manual, PCIe x8 GEN 2 Cable Adapter OSS-PCIe-HIB25-x8-H (Host) OSS-PCIe-HIB25-x8-T (Target)
Table of Contents 1. Overview 1.a. Host cable adapter ................................................................................................................................ 3 1.b. Target cable adapter ............................................................................................................................. 3 1.c. Specifications ........................................................................................................................................ 4 1.d.
1. Overview 1.a. Host cable adapter The host adapter (Part # OSS-PCIe-HIB25 x8-H) installs into the host computer’s slot, allowing communication between a processor and an I/O point. Slot Cover (Also available in low profile height) PCIe x8Connector 1.b. Target cable adapter The target cable adapter (Part# OSS-PCIe-HIB25-x25-x8-T) installs into the target slot of an OSS 2-slot backplane and extends the PCIe bus to a single add-in board installed in the I/O slot of the 2-slot backplane.
1.c. Specifications Dimensions (H x L): 2.2 x 4.5 inches (55 x 114mm) Front Panel Connectors: One PCIe x8 cable connector Front Panel Indicators: Power On / Cable Present LEDs Power Consumption (designed to meet the following conditions) 3.75W typical, 3.3@1.3A Operating Environment (designed to meet the following conditions) Temperature Range: 0° to 50°C (32° to 122°F) Relative Humidity: 10 to 90% non-condensing Shock: 30g acceleration peak (11ms pulse) Vibration: 5-17 Hz 0.
1.d. Block Diagram Clock* Clock* LVPECL Clock Buffer X8 PCIe Tx PCIe Signal Redriver X8 PCIe Rx PCIe Signal Redriver X8 PCIe Tx X8 PCIe Rx +3.3v CPRSNT# LEDs Cable Present/ Pwr Downstream X8 PCI Express Cable Connector One Stop Systems Rev.
2. Initial Set-Up 2.a. Unpacking Instructions 1) If the carton is damaged when you receive it, request that the carrier’s agent be present when you unpack and inspect the equipment. 2) After unpacking, verify that all items listed in the packing list are present. 3) Inspect the equipment for shipping damage. 4) Save all packing material for storage or return shipment of the equipment. 2.b. Installation and Removal 1) Power down the host system.
2.d. Removing the host cable adapter 1) To remove cable pull back on green thumb tab to release metal pins and gently separate. 2) Loosen and remove the screw before removing the Host Cable Adapter from the card slot. 2.e. When using with any third party I/O device: 1) Install the downstream board into the appropriate PCIe slot. 2) Connect the external power source (separate from the host system power supply) to the downstream device if necessary.
4. Ordering Information OSS-PCIe-HIB25-x8-H - One Stop Systems HIB25 x8 host cable adapter. OSS-PCIe-HIB25-x8-T - One Stop Systems HIB25 x8 target cable adapter. OSS-PCIe-HIB25-x4-H – PCIe x4 Gen 2 host cable adapter installs in a x4, x8, x16 expansion slot of a host system to extend the host PCIe bus to an expansion system or PCIe device. OSS-PCIe-HIB25-x4-T – PCIe x4 Gen 2 target cable is only used with the OSS 2-slot PCIe backplane to add a single PCIe card to a host.
Appendix Pin Assignments Connectors PCIe x8 Card Edge Connector The pins are numbered as shown with side A on the top of the centerline on the solder side of the board and side B on the bottom of the centerline on the component side of the board. The PCIe interface pins PETpx, PETnx, PERpx, and PERnx are named with the following convention: “PE” stands for PCIe high speed, “T” for Transmitter, “R” for Receiver, “p” for positive (+), and “n” for negative (-).
29 GND Ground PERp3 30 RSVD Reserved PERn3 31 PRSNT2# Hot-Plug presence detect GND Ground 32 GND Ground RSVD Reserved 33 PETp4 RSVD Reserved 34 PETn4 GND Ground 35 GND Ground PERp4 36 GND Ground PERn4 37 PETp5 38 PETn5 39 GND Ground PERp5 40 GND Ground PERn5 41 PETp6 42 PETn6 43 GND Ground PERp6 44 GND Ground PERn6 45 PETp7 46 PETn7 Transmitter differential pair, Lane 4 Transmitter differential pair, Lane 5 Transmitter differential pair, Lane 6
Notes: 1 Optional signals that are not implemented are to be left as no connects on the board side connector. 2 Reserved signals must be left as no connects on the board side connector. 3 Although support of CWAKE# is optional from the board side connector perspective, an allocated wire is mandated for the cable assembly. 4 Board side pin-out on both sides of the Link is identical. The cable assembly incorporates a null modem for the PCIe transmit and receive pairs.
Signal Descriptions PETp(x) PCI Express Transmit Positive signal of (x) pair. PETn(x) PCI Express Transmit Negative signal of (x) pair. PERp(x) PCI Express Receive Positive signal of (x) pair. PERn(x) PCI Express Receive Negative signal of (x) pair. Cable REFerence CLocK: Provides a reference clock from the host system to the remote system. Side Band ReTurN: return path for single ended signals from remote systems.
