Data Sheet

NDS356AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
Features
_______________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter NDS356AP Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage - Continuous ±20 V
I
D
Maximum Drain Current - Continuous (Note 1a) ±1.1 A
- Pulsed ±10
P
D
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
Publication Order Number:
NDS356AP/D
General Description
SuperSOT
TM
-3 P-Channel logic level enhancement mode
power field effect transistors are produced using ON
Semiconductor's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a
very small outline surface mount package.
-1.1 A, -30 V, R
DS(ON)
= 0.3 @ V
GS
=-4.5 V
R
DS(ON)
= 0.2 @ V
GS
=-10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOT
TM
-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
D
S
G
© 1997 Semiconductor Components Industries, LLC.
October-2017,Rev 3

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