Datasheet

MMBF4391LT1G, SMMBF4391LT1G, MMBF4392LT1G, MMBF4393LT1G
http://onsemi.com
4
Figure 5. Switching Time Test Circuit
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
I
D
, DRAIN CURRENT (mA)
2.0
5.0
3.0
7.0
0.5 1.0 3.0 7.05.0 5030
10
20
0.7 2.0 10 20
, FORWARD TRANSFER ADMITTANCE (mmhos)
fs
V
10
2.0
15
3.0
5.0
7.0
0.5 1.0 3.0 305.00.30.1 100.050.03
V
R
, REVERSE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
T
channel
= 25°C
V
DS
= 15 V
T
channel
= 25°C
(C
ds
is negligible
C
gs
V
DD
V
GG
R
GG
R
T
R
GEN
50 W
V
GEN
R
K
R
D
OUTPUT
INPUT
50
W
50
W
SET V
DS(off)
= 10 V
INPUT PULSE
t
r
≤ 0.25 ns
t
f
≤ 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
R
GG
> R
K
R
D'
= R
D
(R
T
+ 50)
R
D
+ R
T
+ 50
Figure 8. Effect of Gate−Source Voltage
on Drain−Source Resistance
80
120
160
200
50
1.0 3.0
170
5.0
20-10-40
2.0
80 140-70
V
GS
, GATE-SOURCE VOLTAGE (VOLTS)
r
4.00
40
100 mA
125 mA
75 mA50 mA
25 mA
I
DSS
= 10
mA
T
channel
= 25°C
Figure 9. Effect of Temperature on Drain−Source
On−State Resistance
1.8
1.0
2.0
1.2
1.4
1.6
0.8
0.6
0.4
I
D
= 1.0 mA
V
GS
= 0
, DRAIN-SOURCE ON-STATE
DS(on)
RESISTANCE (NORMALIZED)
T
channel
, CHANNEL TEMPERATURE (°C)
1.5
1.0
C
gd
110
6.0 7.0 8.0
0
r , DRAIN-SOURCE ON-STATE
DS(on)
RESISTANCE (OHMS)
MMBF4393
MMBF4392
MMBF4391
NOTE 1
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (−V
GG
). The
Drain−Source Voltage (V
DS
) is slightly lower than Drain Supply
Voltage (V
DD
) due to the voltage divider. Thus Reverse Transfer
Capacitance (C
rss
) of Gate−Drain Capacitance (C
gd
) is charged to
V
GG
+ V
DS
.
During the turn−on interval, Gate−Source Capacitance (C
gs
)
discharges through the series combination of R
Gen
and R
K
. C
gd
must
discharge to V
DS(on)
through R
G
and R
K
in series with the parallel
combination of effective load impedance (R’
D
) and Drain−Source
Resistance (r
DS
). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel
resistance r
DS
is a function of the gate−source voltage. While C
gs
discharges, V
GS
approaches zero and r
DS
decreases. Since C
gd
discharges through r
DS
, turn−on time is non−linear. During turn−off,
the situation is reversed with r
DS
increasing as C
gd
charges.
The above switching curves show two impedance conditions; 1)
R
K
is equal to R
D’
which simulates the switching behavior of
cascaded stages where the driving source impedance is normally the
load impedance of the previous stage, and 2) R
K
= 0 (low
impedance) the driving source impedance is that of the generator.