Data Sheet

© 1983 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HC595 • Rev. 1.0.2 3
MM74HC595 — 8-Bit Shift Register with Output Latches
Pin Configuration
Figure 2. Pin Configuration
Pin Definitions
Pin # Name Description
1 Q
B
Output Bit B
2 Q
C
Output Bit C
3 Q
D
Output Bit D
4 Q
E
Output Bit E
5 Q
F
Output Bit F
6 Q
G
Output Bit G
7 Q
H
Output Bit H
8 GND Ground
9 Q’
H
Serial Data Output
10 SCLR Shift Register Clear
11 SCK Shift Register Clock Input
12 RCK Storage Register Clock Input
13 G Output Enable
14 SER Serial Data Input
15 QA Output Bit A
16 V
CC
Supply Voltage
Truth Table
RCK SCK SCLR G Function
X X X H QA through Q
H
= 3-state
X X L L Shift register clocked; Q’
H
= 0
X
↑
H L Shift register clocked; Q
N
= Q
n-1
, Q
0
= SER
↑
X H L Contents of shift; register transferred to output latches
L = Logic Level LOW
H = Logic Level HIGH
X = Don’t Care
↑ = Transition from LOW to HIGH level