Data Sheet

©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL06XX Rev. 1.0.9 2
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
Truth Table
(Positive Logic)
*Dual channel devices or single channel devices with pin 7 not connected.
A 0.1µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
Input Enable Output
HHL
LHH
HLH
LLH
H* NC* L*
L* NC* H*
Single-channel circuit drawing
(HCPL0600, HCPL0601 and HCPL0611)
Dual-channel circuit drawing
(HCPL0637, HCPL0638 and HCPL0639)
1
2
3
4 5
6
7
8
N/C
_
V
CC
V
E
V
O
GND
+
N/C
V
F
1
2
3
4
5
6
7
8
+
_
V
F1
V
CC
V
01
V
02
GND
V
F2
_
+