Data Sheet

©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL06XX Rev. 1.0.9 11
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
O
Z = 50Ω
Pulse
Generator
tr = 5ns
(V )
E
Input
Monitor
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
t
ELH
bypass
.1μf
Fig. 20 Test Circuit and Waveforms for t
PLH
, t
PHL,
t
r
and t
f
.
Fig. 21 Test Circuit t
EHL
and t
ELH
.
t
1
2
3
4
1
2
3
4
8
7
6
5GND
V
CC
8
7
6
5
Dual Channel
Pulse Gen.
Z
O
= 50 Ω
t
f
= t
r
= 5 ns
Pulse Gen.
t
f
= t
r
= 5 ns
Z
O
= 50 Ω
+5 V
I
F
V
CC
R
M
R
L
.1μf
Bypass
C
L
+5V
47Ω
R
L
Input
Monitoring
Node
Input
Monitor
(I
F
)
Output
(V
O
)
Output V
O
Monitoring
Node
0.1μF
Bypass
C
L
*
GND
Test Circuit for HCPL0600,
HCPL0601 and HCPL0611
Test Circuit for HCPL0637,
HCPL0638 and HCPL0639