Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsInterface ICsInterface IC - analogue switches UMLP 10

October-2017, Rev. 2 FSUSB42/D

FSUSB42 — Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) UART Switch

FSUSB42 — Low-Power, Two-Port, High-Speed,

USB2.0 (480Mbps) UART Switch

Features

 Low On Capacitance: 3.7 pF Typical

 Low On Resistance: 3.9 Ω Typical

 Low Pow er Consumption: 1 μA Maximum

- 15 μA Maximum I

CCT

over an Expanded Voltage

Range (V

=1.8 V, V

=4.4 V)

 Wide -3 db Bandw idth: > 720 MHz

 Packaged in:

- 10-Lead UMLP (1.4 x 1.8 mm)

- 10-Lead MSOP

 8 kV ESD Rating, >16 kV Pow er / GND ESD Rating

 Over-Voltage Tolerance (OVT) on all USB Ports

Up to 5.25 V w ithout External Components

Applications

 Cell phone, PDA, Digital Camera, and Notebook

 LCD Monitor, TV, and Set-Top Box

Description

The FSUSB42 is a bi-directional, low -pow er, tw o-port,

high-speed, USB2.0 sw itch. Configured as a double-

pole, double-throw sw itch (DPDT) sw itch, it is optimized

for sw itching betw een any combination of high-speed

(480 Mbps) or Full-Speed (12 Mbps) sources.

The FSUSB42 is compatible w ith the requirements of

USB2.0 and features an extremely low on capacitance

) of 3.7 pF. The w ide bandw idth of this device

(720 MHz) exceeds the bandw idth needed to pass the

third harmonic, resulting in signals w ith minimum edge

and phase distortion. Superior channel-to-channel

crosstalk also minimizes interference.

The FSUSB42 contains special circuitry on the sw itch

I/O pins for applications w here the V

supply is

pow ered-off (V

=0 V), w hich allow s the device to

w ithstand an over-voltage condition. This device is

designed to minimize current consumption even w hen

the control voltage applied to the SEL pin is low er than

the supply voltage (V

). This feature is especially

valuable to ultra-portable applications, such as cell

phones, allow ing for direct interface w ith the general-

purpose I/Os of the baseband processor. Other

applications include sw itching and connector sharing in

portable cell phones, PDAs, digital cameras, printers,

and notebook computers.

Ordering Information

Part Number

Top Mark

Operating Temperature

Range

Package

FSUSB42UMX

-40 to +85°C

10-Lead, Quad, Ultrathin Molded Leadless Package

(UMLP), 1.4 x 1.8 mm

FSUSB42MUX

FSUSB42

-40 to +85°C

10-Lead, Molded Small-Outline Package (MSOP)

JEDEC MO-187, 3.0 mm Wide

HSD1+

HSD2+

HSD1-

HSD2-

D-

D+

Control

Sel

/OE

Figure 1. Analog Symbol

Summary of content (10 pages)

PAGE 1
Features        Description Low On Capacitance: 3.7 pF Typical Low On Resistance: 3.9 Ω Typical Low Pow er Consumption: 1 μA Maximum - 15 μA Maximum ICCT over an Expanded Voltage Range (V IN=1.8 V, V CC=4.4 V) Wide -3 db Bandw idth: > 720 MHz Packaged in: - 10-Lead UMLP (1.4 x 1.8 mm) - 10-Lead MSOP 8 kV ESD Rating, >16 kV Pow er / GND ESD Rating Over-Voltage Tolerance (OVT) on all USB Ports Up to 5.
PAGE 2
GND 3 HSD1- 4 HSD1+ 5 D- D+ 2 1 VCC 1 10 Sel 2 9 HSD2+ D+ 3 8 HSD2- D- 4 7 HSD1+ GND 5 6 HSD1- 10 Sel 9 Vcc 8 /OE 6 7 HSD2- HSD2+ Figure 2. 10-Lead UMLP (Top-Through View ) Figure 3.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
PAGE 4
All typical value are at TA=25°C unless otherw ise specified. Symbol Parameter Condition V IK Clamp Diode Voltage IIN=-18mA V IH Input Voltage High V IL Input Voltage Low IIN Control Input Leakage V SW=0 to V CC IOZ Off State Leakage 0 Dn, HSD1n, HSD2n 3.6 V IOFF Pow er-Off Leakage Current (All I/O Ports) V SW=0 V to 4.3 V, V CC=0 V Figure 5 RON HS Sw itch On Resistance ∆RON HS Delta RON (6) (7) VCC (V) TA=- 40°C to +85°C Min. Typ. 3.0 -1.2 2.4 to 3.6 1.3 4.3 1.
PAGE 5
All typical value are for V CC=3.3 V at TA=25°C unless otherw ise specified. Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Min. Typ. Max. 2.4 24 40 3.0 to 3.6 13 30 2.4 15 35 3.0 to 3.6 12 25 3.3 0.25 Unit tON Turn-On Time S, /OE to Output RL=50 Ω, CL=5 pF, V SW=0.8 V, Figure 6, Figure 7 tOFF Turn-Off Time S, /OE to Output RL=50 Ω, CL=5 pF, V SW=0.8 V, Figure 6, Figure 7 tPD Propagation Delay tBBM Break-Before-Make RL=50 Ω, CL=5 pF, V SW1=V SW2=0.8 V, Figure 10 2.
PAGE 6
VON I Dn(OFF) NC A HSDn VSW Dn VSW Select GND I ON GND Select R ON = VON / ION V Sel = V Sel = GND **Each switch port is tested separately 0 orV cc Figure 4. On Resistance HSDn Figure 5. Off Leakage tRISE = 2.5ns Dn VSW GND RS 0 orV V cc CL RL tFALL = 2.
PAGE 7
(Continued) tRISE = 2.5ns Vcc HSDn Dn VSW1 GND 10% 0V VOUT CL VSW2 90% Vcc/2 Input - VSel RL V OUT GND GND 0.9*Vout 0.9*Vout RS tBBM VSel RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. GND Figure 10.
PAGE 8
1.40 0.05 C A B 2X 1.80 (9X) 1.70 PIN#1 IDENT 0.563 0.663 0.05 C TOP VIEW 2X 1 2.10 0.50±.05 0.10 C 0.15±.05 0.40 (10X) 0.225 0.08 C SEATING C PLANE 0.025±.025 RECOMMENDED LAND PATTERN SIDE VIEW 9X 0.45 1.45 0.55 1.40±.05 (0.20) 4X 0.40±.05 (9X) 3 0.40 6 DETAIL A 1.80±.05 1 (0.60) 4X PIN#1 IDENT (10X) 0.225 OPTIONAL MINIMIAL TOE LAND PATTERN 10 0.20±.05 (10X) BOTTOM VIEW 1.85 0.40 0.10 C A B 0.05 C NOTES: A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B.
PAGE 9
FSUSB42 — Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) UART Switch Physical Dimensions (Continued) Figure 17. 10-Lead, Molded Sm all Outline Package (MSOP) www.onsemi.
PAGE 10
FSUSB42 — Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) UART Switch ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf.