Data Sheet

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ500L • Rev. 1.0.3 8
FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)
Functional Description
1. Startup and V
CC
Regulation: At startup, an internal
high-voltage current source supplies the internal bias
and charges the external capacitor (C
A
) connected to
the V
CC
pin, as illustrated in Figure 15. An internal high-
voltage regulator (HV/REG) located between the D and
V
CC
pins regulates the V
CC
to be 6.5V and supplies
operating current. Therefore, FSQ500L needs no
auxiliary bias winding.
V
REF
UVLO
HV/REG
6.5V
2
D
3
VCC
C
A
Transformer
ICH
ISTART
Figure 15. Startup Block
2. Feedback Control: FSQ500L employs current mode
control, as shown in Figure 16. An opto-coupler (such as
the FOD817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the R
sense
resistor makes it possible to control the
switching duty cycle. When the reference pin voltage of
the regulator exceeds the internal reference voltage of
2.5V, the opto-coupler LED current increases, pulling
down the feedback voltage and reducing the duty cycle.
This typically happens when the line input voltage
increases or the output load current decreases.
2.1 Pulse-by-Pulse Current Limit: Because current
mode control is employed, the peak current through the
senseFET is limited by the non-inverting input of PWM
comparator (V
FB
*), as shown in Figure 16. Assuming
that 225µA current source flows only through the
internal resistor (8R + R = 12kΩ), the cathode voltage of
diode D2 is about 2.7V. Since D1 is blocked when the
feedback voltage (V
FB
) exceeds 2.7V, the maximum
voltage of the cathode of D2 is clamped at this voltage,
clamping V
FB
*. Therefore, the peak value of the current
through the senseFET is limited.
2.2 Leading-Edge Blanking (LEB): At the instant the
internal senseFET is turned on, a high-current spike
occurs through the senseFET, caused by primary-side
capacitance and secondary-side rectifier reverse
recovery. Excessive voltage across the R
sense
resistor
would lead to incorrect feedback operation in the current
mode PWM control. To counter this effect, the FPS
employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time (t
LEB
= 250ns) after the senseFET turns on.
2
OSC
V
CC
I
DELAY
I
FB
V
SD
R
8R
Gate
driver
OLP
D1 D2
+
V
FB
*
-
V
FB
KA431
C
B
V
O
FOD817A
R
sense
SenseFET
V
CC
Figure 16. Pulse Width Modulation (PWM) Circuit
3. Protection Circuits: The FSQ500L has two self-
protective functions: overload protection (OLP) and
thermal shutdown (TSD). While OLP is implemented as
auto-restart mode, there is no switching when TSD
triggers. Once the overload condition is detected,
switching is terminated, the senseFET remains off, and
HV/REG turns off. This causes V
CC
to fall. When V
CC
falls below the under voltage lockout (UVLO) stop
voltage of 5.0V, the protection is reset and the startup
circuit charges the V
CC
capacitor. When V
CC
reaches the
start voltage of 6.0V, the FSQ500L resumes its normal
operation. If the fault condition is still not removed, the
senseFET and HV/REG remain off and V
CC
drops to
V
STOP
again. In this manner, the auto-restart can
alternately enable and disable the switching of the
power senseFET until the fault condition is eliminated,
as shown in Figure 17.
Because these protection circuits are fully integrated
into the IC without external components, reliability is
improved without increasing cost.
Fault
situation
5.0V
6.0V
V
CC
V
DS
t
OLP
occurs
OLP
removed
Normal
operation
Normal
operation
Power
on
6.5V
Figure 17. Auto Restart Protection Waveforms