Data Sheet
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSQ100 Rev. 1.0.2 8
FSQ100 — Green Mode Fairchild Power Switch (FPS
TM
)
Functional Description
1. Startup: At startup, the internal high-voltage current
source supplies the internal bias and charges the
external V
CC
capacitor, as shown in Figure 14. When
V
CC
reaches 9V, the device starts switching and the
internal high-voltage current source stops charging the
capacitor. The device is in normal operation provided
V
CC
does not drop below 7V. After startup, the bias is
supplied from the auxiliary transformer winding.
V
IN
,dc
Vstr
V
CC
I
STR
9V/ 7V
L
H
Figure 14. Internal Startup Circuit
Calculating the V
CC
capacitor is an important step to
design with the FSQ100. At initial startup, the maximum
value of start operating current I
START
is about 100µA,
which supplies current to UVLO and V
REF
blocks. The
charging current I
VCC
of the V
CC
capacitor is equal to I
STR
– 100µA. After V
CC
reaches the UVLO start voltage, only
the bias winding supplies V
CC
current to the device.
When the bias winding voltage is not sufficient, the V
CC
level decreases to the UVLO stop voltage and the
internal current source is activated again to charge the
V
CC
capacitor. To prevent this V
CC
fluctuation
(charging/discharging), the V
CC
capacitor should be
chosen to have a value between 10µF and 47µF.
Figure 15. Charging V
CC
Capacitor through Vstr
2. Feedback Control: The FSQ100 is a voltage mode
controlled device, as shown in Figure 16. Usually, an
opto-coupler and shunt regulator, like KA431 are used
to implement the feedback network. The feedback
voltage is compared with an internally generated
sawtooth waveform. This directly controls the duty cycle.
When the shunt regulator reference pin voltage exceeds
the internal reference voltage of 2.5V, the opto-coupler
LED current increases, the feedback voltage V
FB
is
pulled down, and it reduces the duty cycle. This
happens when the input voltage increases or the output
load decreases.
4
OSC
V
CC
V
ref
5µA
V
SD
R
Gate
driver
OLP
V
fb
KA431
C
fb
V
O
+
V
fb
400µA
Figure 16. PWM and Feedback Circuit
3. Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, the primary-side
capacitance and secondary-side rectifier diode reverse
recovery typically causes a high-current spike through
the SenseFET. Excessive voltage across the R
SENSE
resistor lead to incorrect pulse-by-pulse current limit
protection. To avoid this, a leading edge blanking (LEB)
circuit disables pulse-by-pulse current-limit protection
block for a fixed time (t
LEB
) after the SenseFET turns on.
4. Protection Circuit: The FSQ100 has protective
functions, such as overload protection (OLP), over
voltage protection (OVP), under-voltage lockout (UVLO),
and thermal shutdown (TSD). Because these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
costs. Once a fault condition occurs, switching is
terminated and the SenseFET remains off. This causes
V
CC
to fall. When V
CC
reaches the UVLO stop voltage
V
STOP
(7V), the protection is reset and the internal high-
voltage current source charges the V
CC
capacitor via the
V
STR
pin. When V
CC
reaches the UVLO start voltage
V
START
(9V), the device resumes normal operation. In
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated.
OSC
4
V
fb
S
R
Q
GATE
DRIVER
OLP, TSD
Protection Block
5 µA 4 0 0µ A
RESET
4. 5 V
OLP
+
-
TSD
S
R
Q
A/R
C
fb
R
Figure 17. Protection Block
V
IN
,dc
V
ST
R
I
STR
J-FET
U VLO
V
re
f
I
ST
A
R T
I
Vcc
= I
STR
-I
ST
A
RT
I
Vc c
=I
STR
- I
ST
A
R T
V
CC
V
ST
A
RT
V
STOP
t
V
CC
V
CC
must not d
r
op
belo
w
V
STOP
Bias
w
inding
voltage
UV LO