Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FPF3040 • Rev. 2.4.3 6
FPF3040 — IntelliMAX™ 18 V-Rated Dual Input Single Output Power-Source-Selector Switch
Electrical Characteristics
V
IN
=4 to 10.5 V, V
BUS
=4 to 6.5 V, T
A
=-40 to 85°C unless otherwise noted. Typical values are at V
IN
=V
BUS
=5 V,
EN=HIGH and T
A
=25°C unless otherwise noted.
Symbol
Parameters
Condition
Min.
Typ.
Max.
Unit
Basic Operation
V
IN
Input Voltage
4.0
10.5
V
V
BUS
4.0
6.5
V
I
Q
Quiescent Current
I
OUT
=0 mA, EN=HIGH,
V
IN
or V
BUS
=5 V
55
120
μA
I
OUT
=0 mA, EN=5 V,
V
IN
and V
BUS
=GND
33
70
μA
R
ON
On Resistance for V
IN
V
IN
=8 V, I
OUT
=200 mA, T
A
=25°C
95
mΩ
V
IN
=5 V, I
OUT
=200 mA, T
A
=25°C
95
150
V
IN
=5 V, I
OUT
=200 mA,
T
A
=25°C to 85°C
(6)
200
On Resistance for V
BUS
V
BUS
=6 V, I
OUT
=200 mA, T
A
=25°C
70
mΩ
V
BUS
=5 V, I
OUT
=200 mA, T
A
=25°C
70
100
V
BUS
=5 V, I
OUT
=200 mA,
T
A
=25°C to 85°C
(6)
140
V
IH
Input Logic High Voltage
V
IN
=4 V~10.5 V, V
BUS
=4 V ~ 6.5 V
1.15
V
V
IL
Input Logic Low Voltage
V
IN
=4 V~10.5 V, V
BUS
=4 V ~ 6.5 V
0.52
V
V
EN(OTG)
EN Voltage in OTG Mode
(6)
V
IN
& V
BUS
=Float or V
IN
& V
BUS
<V
UVLO
2.5
V
R
EN_PD
Pull-Down Resistance at EN
707
1000
1360
kΩ
Protection
V
UVLO
Under-Voltage Lockout
Threshold
V
IN
or V
BUS
Rising
3.05
3.50
4.00
V
V
IN
or V
BUS
Falling
2.55
3.00
3.55
V
V
UVHYS
Under-Voltage Lockout
Hysteresis
0.5
V
V
OVLO
Over-Voltage Lockout Threshold
V
IN
Rising Threshold
10.85
12.00
13.45
V
V
IN
Falling Threshold
11.5
V
V
BUS
Rising Threshold
6.52
7.50
8.32
V
V
BUS
Falling Threshold
7
V
V
OVHYS
Over-Voltage Lockout
Hysteresis
V
IN
0.5
V
V
BUS
0.5
V
T
SDN
Thermal Shutdown Threshold
150
°C
T
SDNHYS
Thermal Shutdown Hysteresis
20
°C
Reverse Current Blocking
I
RCB
V
IN
or V
BUS
Current During RCB
V
OUT
=8 V, V
IN
or V
BUS
=GND
30
μA
Dynamic Characteristics
t
R
V
OUT
Rise Time, V
BUS
(6,7)
V
IN
=V
BUS
=5 V, R
L
=150 Ω, C
L
=4.7 μF,
T
A
=25°C
90
μs
V
OUT
Rise Time, V
IN
(6,7)
50
t
F
V
OUT
Fall Time
(6,7)
1.4
ms
t
TRAN
Transition Delay
(6,7)
50
100
ms
t
SD
Selection Delay
(6,7)
50
μs
Notes:
6. This parameter is guaranteed by characterization and/or design; not production tested.
7. t
SD
/t
TRAN
/t
R
/t
F
are defined in Figure 6.