Data Sheet

Features
Absolute Maximum Ratings T
A
= 25
o
C unless other wise noted
Symbol Parameter FDV301N Units
V
DSS
, V
CC
Drain-Source Voltage, Power Supply Voltage 25 V
V
GSS
, V
I
Gate-Source Voltage, V
IN
8 V
I
D
, I
O
Drain/Output Current - Continuous 0.22 A
0.5
P
D
Maximum Power Dissipation 0.35 W
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient 357 °C/W
25 V, 0.22 A continuous, 0.5 A Peak.
R
DS(ON)
= 5 @ V
GS
= 2.7 V
R
DS(ON)
= 4 @ V
GS
= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.06V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors with one DMOS
FET.
FDV301N
Digital FET ,
N-Channel
General Description
This N-Channel logic level enhancement mode field effect
transistor is produced using ON Semiconductor's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize on-
state resistance. This device has been designed
especially for low voltage applications as a
replacement for digital transistors. Since bias resistors are
not required, this one N-channel FET can replace several
different digital transistors, with different bias resistor values.
Mark:301
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
D
G
S
D
SG
IN
GND
Vcc
INVERTER APPLICATION
OUT
Publication Order Number:
FDV301N/D
©2009 Semiconductor Components Industries, LLC.
October-2017, Rev. 6

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