Data Sheet

FDMF6705B • Rev. 1.0.3 3

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Pin Configuration

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

1 SMOD#

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add

a noise filter capacitor.

2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

Power for gate driver. Minimum 1 µF ceramic capacitor is recommended, connected as close

as possible from this pin to CGND.

4 BOOT

Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect a

bootstrap capacitor from this pin to PHASE.

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

No connect. The pin is not electrically connected internally, but can be connected to VIN for

convenience.

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

VSWH

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point

for the adaptive shoot-through protection.

16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET.

36 GL For manufacturing test only. This pin must float; must not be connected to any pin.

38 THWN#

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the

output is pulled LOW. THWN# does not disable the module.

39 DISB#

Output disable. When LOW, this pin disables power MOSFET switching (GH and GL are held

LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter

capacitor.

40 PWM PWM signal input. This pin accepts a three-state logic-level PWM signal from the controller.