Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsFETsMOSFET 1 N-channel 55 W

tor Components Industries, LLC.

September-2017, Rev. 2

Publication Order Number:

FDD8880/D

FDD8880

N-Channel PowerTrench

MOSFET

30V, 58A, 9mΩ

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using

either synchronous or conventional switching PWM

controllers. It has been optimized for low gate charge, low

DS(ON)

and fast switching speed.

Applications

• DC/DC converters

eatures

•r

(ON)

9mΩ, V

= 10

V, I

35A

•r

(ON)

12mΩ, V

= 4.

5V, I

35A

• High performance trench technology for extremely low

(ON)

•

Low gate charge

• High power and current handling capability

MOSF

ET Maximum Ratings

= 25°

C unless otherwise noted

The

rmal Characteristics

Package Marking and Ordering Information

mbol Parameter Ratings Units

rain to Source Voltage 30 V

te to Source Voltage ±20 V

rain Current

58 A

Continuous (T

= 10V) (Note 1)

Continuous (T

= 4.5V) (Note 1) 51 A

Continuous (T

C, V

10V, with R

θJA

= 52

W) 13 A

Pulsed Figure 4 A

ingle Pulse Avalanche Energy (Note 2) 53 mJ

ower dissipation 55 W

Derate above 25

C0.37W/

, T

perating and Storage Temperature -55 to 175

θJC

hermal Resistance Junction to Case TO-252 2.73

C/W

θJA

hermal Resistance Junction to Ambient TO-252 100

C/W

θJA

hermal Resistance Junction to Ambient TO-252, 1in

opper pad area 52

C/W

vice Marking Device Package Reel Size Tape Width Quantity

FDD8880 FDD8880 TO-252AA 13” 16mm 2500 units

-252

D-

PAK

(TO-252)

• RoHS

Compliant

Summary of content (11 pages)

PAGE 1
FDD8880 FDD8880 N-Channel PowerTrench® MOSFET 30V, 58A, 9mΩ Features General Description • rDS(ON) = 9mΩ, VGS = 10V, ID = 35A This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. • rDS(ON) = 12mΩ, VGS = 4.
PAGE 2
Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 24V VGS = 0V TC = 150oC VGS = ±20V 30 - - V - - 1 - - 250 µA - - ±100 nA V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance 1.2 - 2.5 ID = 35A, VGS = 10V VGS = VDS, ID = 250µA - 0.007 0.009 ID = 35A, VGS = 4.
PAGE 3
FDD8880 Typical Characteristics TC = 25°C unless otherwise noted 1.2 60 1.0 50 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER CURRENT LIMITED BY PACKAGE 0.8 0.6 0.4 40 VGS = 10V 30 VGS = 4.5V 20 10 0.2 0 0 0 25 50 75 100 150 125 25 175 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.
PAGE 4
FDD8880 Typical Characteristics TC = 25°C unless otherwise noted 1000 IAS, AVALANCHE CURRENT (A) 500 ID, DRAIN CURRENT (A) 10µs 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC DC 1 0.01 0.1 1 60 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 0.
PAGE 5
FDD8880 Typical Characteristics TC = 25°C unless otherwise noted 1.10 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 0.4 -80 0 -40 40 80 120 160 1.05 1.00 0.95 0.90 -80 200 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature Figure 12.
PAGE 6
FDD8880 Test Circuits and Waveforms VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18.
PAGE 7
FDD8880 Thermal Resistance vs. Mounting Pad Area ( T JM – TA ) P DM = ----------------------------Rθ JA (EQ. 1) In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.
PAGE 8
LDRAIN DPLCAP DRAIN 2 5 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 33.15 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 RLDRAIN RSLC1 51 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.
PAGE 9
FDD8880 SABER Electrical Model rev April 2004 template FDD8880 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-12,ikf=10,nl=1.01,rs=3.76e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-17,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=2.0,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.5,kp=170,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.69,kp=0.
PAGE 10
th JUNCTION FDD8880T CTHERM1 TH 6 8e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2.5e-3 CTHERM4 4 3 2.6e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 1.5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 1.44e-1 RTHERM2 6 5 1.9e-1 RTHERM3 5 4 3.0e-1 RTHERM4 4 3 4.0e-1 RTHERM5 3 2 5.7e-1 RTHERM6 2 TL 5.8e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD8880T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =8e-4 ctherm.ctherm2 6 5 =1e-3 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.6e-3 ctherm.
PAGE 11
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