Data Sheet

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November-2017, Rev. 2 FAN7930C/D

FAN7930C — Critical Conduction Mode PFC Controller

FAN7930C

Critical Conduction Mode PFC Controller

Features

 PFC-Ready Signal

 V

-Absent Detection

 Maximum Sw itching Frequency Limitation

 Internal Soft-Start and Startup w ithout Overshoot

 Internal Total Harmonic Distortion (THD) Optimizer

 Precise Adjustable Output Over-Voltage Protection

 Open-Feedback Protection and Disable Function

 Zero-Current Detector (ZCD)

 150 μs Internal Startup Timer

 MOSFET Over-Current Protection (OCP)

 Under-Voltage Lockout w ith 3.5 V Hysteresis

 Low Startup and Operating Current

 Totem-Pole Output w ith High State Clamp

 +500/-800 mA Peak Gate Drive Current

 8-Pin, Small Outline Package (SOP)

Applications

 Adapter

 Ballast

 LCD TV, CRT TV

 SMPS

Description

The FA N7930C is an active pow er factor correction

(PFC) controller for boost PFC applications that operate

in critical conduction mode (CRM). It uses a voltage-

mode PWM that compares an internal ramp signal w ith

the error amplifier output to generate a MOSFET turn-off

signal. Because the voltage-mode CRM PFC controller

does not need rectified AC line voltage information, it

saves the pow er loss of an input voltage-sensing netw ork

necessary for a current-mode CRM PFC controller.

FA N7930C provides over-voltage protection (OVP),

open-feedback protection, over-current protection

(OCP), input-voltage-absent detection, and under-

voltage lockout protection (UVLO). The PFC-ready pin

can be used to trigger other pow er stages w hen PFC

output voltage reaches the proper level w ith hysteresis.

The FAN7930C can be disabled if the INV pin voltage is

low er than 0.45 V and the operating current decreases

to a very low level. Using a new variable on-time control

method, total harmonic distortion (THD) is low er than in

conventional CRM boost PFC ICs.

Related Resources

AN-8035 — Design Consideration for Boundary

Conduction Mode PFC Using FAN7930

Ordering Information

Part Number

Operating

Temperature Range

Top Mark

Package

Packing

Method

FAN7930CMX-G

-40 to +125°C

FAN7930C

8-Lead, Small Outline Package (SOP)

Tape & Reel

Summary of content (22 pages)

PAGE 1
Features Description                The FA N7930C is an active pow er factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode ( CRM). It uses a voltagemode PWM that compares an internal ramp signal w ith the error amplifier output to generate a MOSFET turn-off signal.
PAGE 2
FAN7930C — Critical Conduction Mode PFC Controller Application Diagram DC OUTPUT Vcc FAN7930C line filter AC INPUT 8 VCC 5 ZCD 3 COMP 2 Out RDY 7 CS 4 INV 1 GND 6 PFC ready Figure 1. Typical Boost PFC Application Internal Block Diagram VCC H:open VREF 2.5VREF VBIAS Internal Bias ZCD Clamp Circuit VCC 5 reset 8 VCC 7 OUT 4 CS 6 GND VZ + VTH(S/S) 8.
PAGE 3
VCC OUT GND ZCD FAN7930C 8-SOP INV Figure 3. RDY COMP CS Pin Configuration (Top View ) Pin Definitions Pin # Name Description 1 INV This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5 V. 2 RDY This pin is used to detect PFC output voltage reaching a pre-determined value. When output voltage reaches 89% of rated output voltage, this pin is pulled HIGH, w hich is an (open-drain) output type.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol V CC Parameter Min. Max.
PAGE 5
V CC = 14 V and TA = -40°C~+125°C, unless otherw ise specified. Symbol Parameter Conditions Min. Typ. Max. Unit V CC Section V START Start Threshold Voltage V CC Increasing 11 12 13 V V STOP Stop Threshold Voltage V CC Decreasing 7.5 8.5 9.5 V HY UVLO UVLO Hysteresis 3.0 3.5 4.0 V 20 22 24 V 20 V VZ Zener Voltage V OP Recommended Operating Range ICC=20 mA 13 Supply Current Section ISTART Startup Supply Current V CC=V START-0.
PAGE 6
V CC = 14 V and TA = -40°C~+125°C, unless otherw ise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 1.35 1.50 1.65 V 0.05 0.10 0.15 V 5.5 6.2 7.5 V 0 0.65 1.00 V -1.0 -0.1 Zero-Current Detect Section V ZCD HY ZCD ( ) Input Voltage Threshold 4 ( ) Detect Hysteresis 4 V CLAMPH Input High Clamp Voltage IDET=3 mA V CLAMPL Input Low Clamp Voltage IDET= -3 mA IZCD,BS Input Bias Current IZCD,SR Source Current Capability 4 V ZCD=1 V~5 V 1.
PAGE 7
Function PFC Ready Pin Frequency Limit FAN7530 None None FAN7930C Integrated Integrated FAN7930C Advantages       V IN-Absent Detection Soft-Start and Startup w ithout Overshoot None None Integrated Integrated     Control Range Compensation None Integrated THD Optimizer External Internal TSD None 140°C w ith 60°C Hysteresis     No External Circuit for PFC Output UVLO Reduce Pow er Loss and BOM Cost Caused by PFC Out UVLO Circuit Versatile Open-Drain Pin Abnormal CCM
PAGE 8
Figure 4. Voltage Feedback Input Threshold 1 (V REF1) vs. T A Figure 5. Start Threshold Voltage (V START) vs. T A Figure 6. Stop Threshold Voltage (V STOP) vs. TA Figure 7. Startup Supply Current (ISTART) vs. T A Figure 8. Operating Supply Current (I OP) vs. T A Figure 9. Output Upper Clam p Voltage (V EAH) vs. T A www.onsemi.
PAGE 9
Figure 10. Zero Duty Cycle Output Voltage (V EAZ) vs. T A Figure 11. Maxim um On-Tim e Program 1 (t ON,MAX1) vs. T A Figure 12. Maxim um On-Tim e Program 2 (t ON,MAX2) vs. T A Figure 13. Current-Sense Input Threshold Voltage Lim it (V CS) vs. T A Figure 14. Input High Clam p Voltage (V CLAMPH) vs. T A Figure 15. Input Low Clam p Voltage (V CLAMPL) vs. T A www.onsemi.
PAGE 10
Figure 16. Output Voltage High (V OH) vs. TA Figure 17. Output Voltage Low (V OL) vs. T A Figure 18. Restart Tim er Delay (t RST) vs. TA Figure 19. Output Ready Voltage (V RDY) vs. T A Figure 20. Output Saturation Voltage (V RDY,SAT) vs. T A Figure 21. OVP Threshold Voltage (V OVP) vs. TA www.onsemi.
PAGE 11
VOUTPFC UVLO OVP 2.5 2.675 0.35 0.45 2.675V/2.5V + disable + 0.45V/0.35V + INV open VOUTPFC 2.240V/2.051V - disable - PFC Inductor 2.5V INV high - VINPFC + 1. Startup: Nor mally, supply voltage (V CC) of a PFC block is fed from the additional pow er supply, w hich can be called standby pow er. Without this standby pow er, auxiliary w inding for zero current detection can be used as a supply source.
PAGE 12
VSTART VSTOP PFC operation 5V VINV(=VPFCOUT) unw anted burst operation easily happens at light load and audible noise may be generated from the boost inductor or inductor at input filter. Different from the other converters, burst operation in PFC block is not needed because the PFC block itself is nor mally disabled dur ing standby mode.
PAGE 13
IDIODE IMOSFET VOUT VIN VACIN VCC VAUX & VZCD tRESTART VAUX 150 s VZCD MOSFET gate 6.2V 0.65V t Figure 28. ZCD after COMPARATOR Auxiliary Voltage Depends on MOSFET Sw itching t Figure 30. The aux iliary w inding voltage is used to check the boost inductor current zero instance.
PAGE 14
6.2V THD-Optimized Sawtooth Generator 1V + Sawtooth MOSFET Off ICOMP INV - 1 VREF Stair Step Powering + C2 R1 250 mho C1 2.6V 3 2.5V COMP 2.4V Sourcing Clamp Circuit 115 mho Control Circuit Unlike a conventional voltage- mode PWM controller, FA N7930C turns on the MOSFET at the falling edge of ZCD signal. The “ ON” instant is deter mined by the external signal and the turn-on time lasts until the error amplifier output (V COMP) and saw tooth w aveform meet.
PAGE 15
IIN IINDUCTOR IMOSFET IDIODE VZCD INEGATIVE VOUT 1.5V Conventional Controller Startup Overshoot 1.4V 150ns Startup Overshoot Control MOSFET gate ON ON Control Transition t Figure 38. VCOMP Input and Output Current Near Input Voltage Peak IIN Depends on Load IINDUCTOR Internal Controller t Figure 37. VZCD INEGATIVE Startup w ithout Overshoot 9. T HD Optim ization: Total Har monic Distortion (THD) is the factor that dictates how closely input current shape matches sinusoidal form.
PAGE 16
FAN7930C — Critical Conduction Mode PFC Controller VOUT VIN VAUX RZCD Though VIN is eliminated, operation of controller is normal due to the large bypass capacitor. Vcc THD Optimizer N 1 VAUX ZCD 5 MOSFET gate Zero-Current Detect DMAX fMIN VCOMP VREF IMOT IDS reset High drain current! CMOT Sawtooth Generator t Figure 40. VZCD tON Figure 42. Circuit of THD Optim izer tON is typically constant over 1 AC line frequency, but tON is changed by ZCD voltage.
PAGE 17
PFC block nor mally handles high sw itching current and the voltage low energy signal path can be affected by the high energy path. Cautious PCB layout is mandatory for stable operation. 1. 2. The gate drive path should be as short as possible. The closed-loop that starts from the gate driver, MOSFET gate, and MOSFET source to ground of PFC controller should be as close as possible. This is also crossing point betw een pow er ground and signal ground.
PAGE 18
Application Device Input Voltage Range Rated Output Power Output Voltage (Maximum Current) LCD TV Pow er Supply FAN7930C 90-265 V AC 195 W 390 V (0.5 A) Features    Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input. Pow er factor at rated load is higher than 0.98 at universal input. Total Harmonic Distortion (THD) at rated load is low er than 15% at universal input.
PAGE 19
EER3019N Naux 9,10 1,2 9,10 1,2 NP Naux 6,7 6,7 Np 3,4 3,4 Figure 46. Transform er Schem atic Diagram Winding Specification Position Bottom No Pin (S → F) Wire Turns Winding Method Np 3, 4 → 1, 2 0.1φ×50 39 Solenoid Winding Insulation: Polyester Tape t = 0.05mm, 3 Layers NAUX Top 9,10 → 6,7 0.3φ 5 Solenoid Winding Insulation: Polyester Tape t = 0.
PAGE 20
Part # Value Note Part # Value Note Resistor Sw itch R101 1 MΩ 1W R102 330 kΩ 1/2W Q101 FCPF20N60 20 A, 600 V, SuperFET® R103 10 kΩ 1W D101 1N4746 1 W, 18 V, Zener Diode R104 30 kΩ 1/4W D102 UF4004 1 A, 400 V Glass Passivated High-Efficiency Rectifier R107 10 kΩ 1/4W D103 1N4148 1 A, 100 V Small-Signal Diode R108 4.
PAGE 21
5.00 4.80 A 0.65 3.81 8 5 B 1.75 6.20 5.80 PIN ONE INDICATOR 4.00 3.80 1 5.60 4 1.27 (0.33) 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 0.25 0.19 C 1.75 MAX 0.10 0.51 0.33 OPTION A - BEVEL EDGE 0.50 x 45° 0.25 R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.40 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 47. A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA.
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FAN7930C — Critical Conduction Mode PFC Controller ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf.