Data Sheet

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21
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
Thermal Guidelines
Gate drivers used to sw itch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
pow er. It is important to determine the driver pow er
dissipation and the resulting junction temperature in the
application to ensure that the part is operating w ithin
acceptable temperature limits.
The total pow er dissipation in a gate driver is the sum of
tw o components, P
GATE
and P
DYNAMIC
:
P
TOTAL
= P
GATE
+ P
DYNAMIC
(1)
Gate Dr iving Loss: The most significant pow er loss
results from supplying gate current (charge per unit
time) to sw itch the load MOSFET on and off at the
sw itching frequency. The pow er dissipation that
results from driving a MOSFET at a specified gate-
source voltage, V
GS
, w ith gate charge, Q
G
, at
sw itching frequency, f
SW
, is determined by:
P
GATE
= Q
G
• V
GS
• f
SW
• n (2)
n is the number of driver channels in use (1 or 2).
Dynamic Pre-drive / Shoot-through Current: A
pow er loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-dow n resistors, can be
obtained using the “I
DD
( No-Load) vs. Frequency”
graphs in Typical Performance Character istics to
determine the current I
DYNAMIC
draw n from V
DD
under actual operating conditions:
P
DYNAMIC
= I
DYNAMIC
• V
DD
• n (3)
Once the pow er dissipated in the driver is determined,
the driver junction rise w ith respect to circuit board can
be evaluated using the follow ing thermal equation,
assuming
ψ
JB
w as determined for a similar thermal
design (heat sinking and air flow ):
T
J
= P
TOTAL
•
ψ
JB
+ T
B
(4)
w here:
T
J
= driver junction temperature
ψ
JB
= (psi) thermal characterization parameter
relating temperature rise to total pow er
dissipation
T
B
= board temperature in location defined in Note
2 under Thermal Resistance table.
In the forw ard converter w ith synchronous rectifier
show n in the typical application diagrams, the
FDMS8660S is a reasonable MOSFET selection. The
gate charge for each SR MOSFET w ould be 60 n C w ith
V
GS
= V
DD
= 7V. At a sw itching frequency of 500 kHz,
the total pow er dissipation is:
P
GATE
= 60 nC • 7 V • 500 kHz • 2 = 0.42 W (5)
P
DYNAMIC
= 3 mA • 7 V • 2 = 0.042 W (6)
P
TOTAL
= 0.46 W (7)
The SOIC-8 has a junction-to-board thermal
characterization parameter of
ψ
JB
= 43°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along w ith airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; w ith 80%
derating, T
J
w ould be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
T
B
= T
J
- P
TOTAL
•
ψ
JB
(8)
T
B
= 120°C – 0.46 W • 43°C/W = 100°C (9)
For comparison, replace the SOIC-8 used in the
previous example w ith the 3x3 mm MLP package w ith
ψ
JB
= 3.5°C/ W. The 3x3 mm MLP package could
operate at a PCB temperature of 118°C, w hile
maintaining the junction temperature below 120°C. Th is
illustrates that the physically smaller MLP package w ith
thermal pad offers a more conductive path to remove
the heat from the driver. Consider tradeoffs betw een
reducing overall circuit size w ith junction temperature
reduction for increased reliability.