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FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers

FAN3226 / FAN3227 / FAN3228 / FAN3229 D l 2 A Hi h Sd L Sid G t D i

Applications Information

Input Thresholds

Each member of the FAN322x driver family consists of

tw o identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FA N3226 and

FAN3227, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. Th e EN

pin has TTL thresholds for parts w ith either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. If the channel A and channel B

inputs and outputs are connected in parallel to increase

the driver current capacity, ENA and ENB should be

connected and driven together.

The FA N322x family offers versions in either TTL or

CMOS input thresholds. In the FA N322x T, the input

thresholds meet industry-standard TTL-logic thresholds

independent of the V

voltage, and there is a

hysteresis voltage of approximately 0.4 V. These levels

permit the inputs to be driven from a range of input logic

signal levels for w hich a voltage over 2 V is considered

logic high. The driving signal for the TTL inputs should

have fast rising and falling edges w ith a slew rate of

6 V/µs or faster, so a rise time from 0 to 3.3 V should be

550 ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

In the FAN322xC, the logic input thresholds are

dependent on the V

level and, w ith V

of 12 V, the

logic rising edge threshold is approximately 55% of V

and the input falling edge threshold is approximately

38% of V

. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V

. The

CMOS inputs can be used w ith relatively s low edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

w indow . This allow s setting precise timing intervals by

fitting an R-C circuit betw een the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay betw een the

controlling signal and the OUT pin of the driver.

Static Supply Current

In the I

(static) typical performance characteristics

(see Figure 13 - Figure 15 and Figure 20 - Figure 22),

the curve is produced w ith all inputs / enables floating

(OUT is low ) and indicates the low est static I

current

for the tested configuration. For other states, additional

current flows through the 100 kΩ resistors on the inputs

and outputs show n in the block diagram of each part

(see Figure 5 - Figure 8). In these cases, the actual

static I

current is the value obtained from the curves

plus this additional current.

MillerDrive™ Gate Drive Technology

FAN322x gate drivers incorporate the MillerDrive™

architecture show n in Figure 48. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a w ide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT sw ings betw een 1/3 to 2/3

and the MOS devices pull the output to the high or

low rail.

The purpose of the MillerDrive™ architecture is to

speed up sw itching by providing high current during the

Miller plateau region w hen the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications that have zero voltage sw itching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast sw itching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is sw itched on.

The output pin slew rate is determined by V

voltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slow er rise or fall time

at the MOSFET gate is needed.

Input

stage

OUT

Figure 48. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN322x startup logic is optimized to drive ground-

referenced N-channel MOSFETs w ith an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V

is rising, yet below the

3.9 V operational level, this circuit holds the output low ,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2 V before the

part shuts dow n. This hysteresis helps prevent chatter

when low V

supply voltages have noise from the

pow er sw itching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver w ould turn the P-channel

MOSFET on w ith V

below 3.9 V.