Data Sheet

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN3180 • Rev. 1.0.3 12
FAN3180 — Single 2-A Low-Side Driver with 3.3-V LDO
During startup, 3V3 is internally monitored by a signal
that prevents the output from switching until 80 µs after
3V3 is within regulation. Therefore, if V
DD
is applied
quickly and there is a valid V
IN
signal, there are no
output pulses until 80 µs after 3V3 is in full regulation,
even though V
DD
>UVLO
ON
.
Figure 27. V
DD
>UVLO
ON
Before 3V3
Conversely, if V
DD
is applied slowly (UVLO
ON
occurs
after 80 µs 3V3 startup) and there is a valid V
IN
signal,
there are no output pulses until V
DD
reaches UVLO
ON
,
even though 3V3 is in full regulation.
Figure 28. 3V3 Before V
DD
>UVLO
ON
Two conditions are required for valid output switching:
1. V
DD
>UVLO
ON
,
2. 3V3 in regulation.
Startup Logic
When V
DD
>UVLO
ON
and 3V3 is in regulation, output
switching begins following the first valid rising edge of
the V
IN
signal.
Figure 29. V
DD
Applied when V
IN
HIGH
Figure 30. V
DD
Applied when V
IN
LOW
Holding off the output until the first valid rising edge
prevents an incomplete pulse from appearing on the
output, as shown in Figure 29.
Shutdown
When V
DD
is removed and falls below UVLO
OFF
, the
output immediately terminates switching regardless of
the V
IN
signals.
Figure 31. Turn-Off During V
IN
HIGH
Figure 32. Turn-Off During V
IN
LOW