Data Sheet

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FAN3180 • Rev. 1.0.3 11

FAN3180 — Single 2-A Low-Side Driver with 3.3-V LDO

Application Information

Input Stage

The FAN3180 input thresholds between 2 V and 5 V

meet industry-standard TTL-logic thresholds,

independent of the V

voltage. The input rising-edge

threshold is approximately 50% of 3.3 V and the input

falling-edge threshold is approximately 30% of 3.3 V. The

TTL-like input configuration offers a hysteresis voltage of

approximately 0.7 V. These levels permit the inputs to be

driven from a range of input logic signal levels for which a

voltage over 2 V is considered logic HIGH. The driving

signal for the TTL inputs should have fast rising and

falling edges with a slew rate of 6 V/µs or faster, so the

rise time from 0 to 3.3 V should be 550 ns or less. With

reduced slew rate, circuit noise could cause the driver

input voltage to exceed the hysteresis voltage and

retrigger the driver input, causing erratic operation.

MillerDrive™ Gate Drive Technology

The FAN3180 incorporates the MillerDrive™

architecture shown in Figure 25 for the output stage, a

combination of bipolar and MOSFET devices capable of

providing large currents over a wide range of supply-

voltage and temperature variations. The bipolar devices

carry the bulk of the current as OUT swings between 1/3

to 2/3 V

and the MOSFET devices pull the output to

the high or low rail.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing the highest current

during the Miller plateau region when the gate-drain

capacitance of the MOSFET is being charged or

discharged as part of the turn-on / turn-off process. For

applications with Zero-Voltage Switching (ZVS) during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast switching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is switched on.

The output-pin slew rate is determined by V

voltage

and the load on the output. It is not adjustable, but if a

slower rise or fall time at the MOSFET gate is needed, a

series resistor can be added.

Input

Stage

OUT

Figure 25. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN3180 startup logic is optimized to drive ground

referenced N-channel MOSFETs with an under-voltage

lockout (UVLO) function to ensure the IC starts up in an

orderly fashion. When V

is rising, yet below the 4.5 V

operational level, this circuit holds the output LOW,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2 V before the

part shuts down. This hysteresis helps prevent chatter

when low V

supply voltages have noise from the

power switching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver would turn the P-channel

MOSFET on with V

below 4.5 V.

Bypass Capacitor Guidelines

To enable this IC to turn a power device on quickly, a

local, high-frequency, bypass capacitor, C

BYP,

with low

ESR and ESL should be connected between the VDD

and GND pins with minimal trace length. This capacitor

is in addition to bulk electrolytic capacitance of 10µF to

47 µF often found on driver and controller bias circuits.

A typical criterion for choosing the value of C

BYP

is to

keep the ripple voltage on the V

supply ≤5%. Often

this is achieved with a value ≥ 20 times the equivalent

load capacitance C

EQV

, defined here as Q

gate

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics such as X5R and

X7R, which have good temperature characteristics and

high pulse current capability.

If circuit noise affects normal operation, the value of

BYP

may be increased to 50-100 times C

EQV

or C

BYP

may be split into two capacitors. One should be a larger

value, based on equivalent load capacitance, and the

other a smaller value, such as 1-10 nF, mounted closest

to the VDD and GND pins to carry the higher-frequency

components of the current pulses.

3V3 Internal Regulator

For microcontroller or ASIC applications requiring a low-

power 3.3-V bias, FAN3180 includes an internal 3.3-V

regulator. The regulator is rated to source up to 15 mA

with a typical current limit of 35 mA, shown in Figure 26.

3.290

3.291

3.292

3.293

3.294

3.295

3.296

3.297

3.298

3.299

3.300

0 5 10 15 20 25 30 35 40

3V3 (V)

I(3V3) (mA)

3V3 vs I(3V3)

VDD=12V, CLoad = 1nF, VIN = 3.3V, 10kHz, 50%

Figure 26. 3V3 Regulation vs. I

(3V3)

During normal operation, a 0.1 µF ceramic capacitor

should be connected between 3V3 and GND.