Data Sheet

www.onsemi.com
2
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Figure 1. 6-Lead MLP (Top View)
Figure 2. SOT23-5 (Top View)
Ordering Information
Part Number
Input
Threshold
Package Packing Method Quantity / Reel
FA N3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000
FA N3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000
FA N3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000
FA N3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000
Package Outlines
1 6
52
43
IN+
AGND
VDD
IN−
PGND
OUT
1
2
3
5
4
VDD
GND
IN+ IN−
OUT
Figure 3. 6-Lead MLP (Top View)
Figure 4. SOT23-5 (Top View)
Thermal Characteristics
(1)
Package
Θ
JL
(2)
Θ
JT
(3)
Θ
JA
(4)
Ψ
JB
(5)
Ψ
JT
(6)
Units
6-Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 °C/W
SOT23-5 56 99 157 51 5 °C/W
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Θ
JL
): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
3. Theta_JT (Θ
JT
): Thermal resistance betw een the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (Θ
JA
): Thermal resistance betw een junction and ambient, dependent on the PCB design, heat sinking, and
airflow . The value given is for natural convection w ith no heatsink using a 2SP2 board, as specified in JEDEC
standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Ps i_JB (Ψ
JB
): Thermal characterization parameter providing correlation betw een semiconductor junction temperature
and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6
package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either
end of the package. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.
6. Ps i_JT (Ψ
JT
): Thermal characterization parameter providing correlation betw een the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.