Data Sheet

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FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

Layout and Connection Guidelines

The FAN3100 incorporates fast-reacting input circuits,

short propagation delays, and pow erful output stages

capable of delivering current peaks over 2 A to facilitate

voltage transition times from under 10 ns to over 100 ns.

The follow ing layout and connection guidelines are

strongly recommended:

 Keep high-current output and pow er ground paths

separate from logic input signals and signal ground

paths. This is especially critical w hen dealing w ith

TTL-level logic thresholds.

 Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-speed

sw itching, w hile reducing the loop area that can

radiate EMI to the driver inputs and other surrounding

circuitry.

 The FAN3100 is available in tw o packages w ith

slightly different pinouts, offering similar

performance. In the 6-pin MLP package, Pin 2 is

internally connected to the input analog ground and

should be connected to pow er ground, Pin 5, through

a short direct path underneath the IC. In the 5-pin

SOT23, the internal analog and pow er ground

connections are made through separate, individual

bond w ires to Pin 2, w hich should be used as the

common ground point for pow er and control signals.

 Many high-speed pow er circuits can be susceptible

to noise injected from their ow n output or other

external sources, possibly causing output re-

triggering. These effects can be especially obvious if

the circuit is tested in breadboard or non-optimal

circuit layouts w ith long input, enable, or output

leads. For best results, make connections to all pins

as short and direct as possible.

 The turn-on and turn-off current paths should be

minimized as discussed in the follow ing sections.

Figure 43 show s the pulsed gate drive current path w hen

the gate driver is supplying gate charge to turn the

MOSFET on. The current is supplied from the local bypass

capacitor, C

BYP

, and flow s through the driver to the

MOSFET gate and to ground. To reach the high peak

currents possible, the resistance and inductance in the

path should be minimized. The localized C

BYP

acts to

contain the high peak current pulses w ithin this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

PWM

BYP

FAN3100

Figure 43. Current Path for MOSFET Turn-On

Figure 44 show s the current path w hen the gate driver

turns the MOSFET off. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

PWM

BYP

FAN3100

Figure 44. Current Path for MOSFET Turn-Off

Truth Table of Logic Operation

The truth table indicates the operational states using the

dual-input configuration. In a non-inverting driver

configuration, the IN- pin should be a logic LOW signal. If

the IN- pin is connected to logic HIGH, a disable function is

realized, and the driver output remains LOW regardless of

the state of the IN+ pin.

IN+

IN-

OUT

In the non-inverting driver configuration in Figure 45, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

HIGH to disable the driver and the output remains LOW,

regardless of the state of the IN+ pin.

VDD

GND

IN+

OUT

PWM

FAN3100

Figure 45. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application show n in Figure 46, the

IN+ pin is tied HIGH. Pulling the IN+ pin to GND forces the

output LOW, regardless of the state of the IN- pin.

VDD

GND

IN-

IN+

OUT

PWM

FAN3100

Figure 46. Dual-Input Driver Enabled,

Inverting Configuration