Data Sheet

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December-2017, Rev . 2 FAN3100T/D

FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver

FAN3100C / FAN3100T

Single 2 A High-Speed, Low-Side Gate Driver

Features



3 A Peak Sink/Source at V

= 12 V

 4.5 to 18 V Operating Range

 2.5 A Sink / 1.8 A Source at V

OUT

= 6 V

 Dual-Logic Inputs Allow Configuration as

Non-Inverting or Inverting w ith Enable Function

 Internal Resistors Turn Driver Off If No Inputs

 13 ns Typical Rise Time and 9 ns Typical Fall-Time

w ith 1 nF Load

 Choice of TTL or CMOS Input Thresholds

 MillerDrive™ Technology

 Typical Propagation Delay Time Under 20 ns w ith

Input Falling or Rising

 6-Lead, 2x2 mm MLP or 5-Pin, SOT23 Packages

 Rated fr om –40°C to 125°C Ambient

Applications



Sw itched-Mode Pow er Supplies (SMPS)

 High-Efficiency MOSFET Sw itching

 Synchronous Rectifier Circuits

 DC-to-DC Converters

 Motor Control

Description

The FAN3100 2 A gate driver is designed to drive an N-

channel enhancement-mode MOSFET in low -side

sw itching applications by providing high peak current

pulses during the short sw itching intervals. The driver is

available w ith either TTL (FAN3100T) or CMOS

(FAN3100C) input thresholds. Internal circuitry provides

an under-voltage lockout function by holding the output

LOW until the supply voltage is w ithin the operating range.

The FAN3100 delivers fast MOSFET sw itching

performance, w hich helps maximize efficiency in high-

frequency pow er converter designs.

FAN3100 drivers incorporate MillerDrive™ architecture for

the final output stage. This bipolar-MOSFET combination

provides high peak current during the Miller plateau stage

of the MOSFET turn-on / turn-off process to minimize

sw itching loss, w hile providing rail-to-rail voltage sw ing

and reverse current capability.

The FAN3100 also offers dual inputs that can be

configured to operate in non-inverting or inverting mode

and allow implementation of an enable function. If one or

both inputs are left unconnected, internal resistors bias

the inputs such that the output is pulled LOW to hold the

pow er MOSFET off.

The FAN3100 is available in a lead-free finish, 2x2 mm, 6-

lead, Molded Leadless Package (MLP) for the smallest

size w ith excellent thermal performance; or industry-

standard, 5-pin, SOT23.

Functional Pin Configurations

1 6

IN+

AGND

VDD

IN-

PGND

OUT

VDD

GND

IN+ IN−

OUT

Summary of content (21 pages)

PAGE 1
Features Description     The FAN3100 2 A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low -side sw itching applications by providing high peak current pulses during the short sw itching intervals. The driver is available w ith either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output LOW until the supply voltage is w ithin the operating range.
PAGE 2
Figure 2. SOT23-5 (Top View ) Ordering Information Part Number Input Threshold Package Packing Method Quantity / Reel FAN3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000 FAN3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000 Package Outlines IN+ 1 VDD 1 GND 2 IN+ 3 5 OUT 4 IN− 6 IN− AGND 2 5 PGND VDD 3 4 OUT Figure 3. 6-Lead MLP (Top View ) Figure 4.
PAGE 3
SOT23 MLP Name Pin # Pin # 1 3 VDD 2 AGND 2 GND Pin Description Supply Voltage. Provides pow er to the IC. Analog ground for input signals (MLP only). Connect to PGND underneath the IC. Ground (SOT-23 only). Common ground reference for input and output circuits. 3 1 IN+ Non-Inverting Input. Connect to VDD to enable output. 4 6 IN- Inverting Input. Connect to AGND or PGND to enable output.
PAGE 4
1 VDD 5 OUT 2 GND 3 VDD 4 OUT 5 PGND UVLO 100kΩ VDD_OK IN+ 3 100kΩ 100kΩ IN- 4 Figure 5. Sim plified Block Diagram (SOT23 Pin-out) UVLO 100kΩ VDD_OK IN+ 1 100kΩ 100kΩ IN- 6 AGND 2 0.4Ω Figure 6. Sim plified Block Diagram (MLP Pin-out) www.onsemi.
PAGE 5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.
PAGE 6
Unless otherw ise noted, V DD = 12 V, TJ = -40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply V DD IDD Operating Range 4.5 (8) Supply Current Inputs/EN Not Connected 18.0 V FAN3100C 0.20 0.35 mA FAN3100T 0.50 0.80 mA V ON Turn-On Voltage 3.5 3.9 4.3 V V OFF Turn-Off Voltage 3.3 3.7 4.
PAGE 7
90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 tRISE VINH VINL tD2 tD1 tFALL Figure 7. Non-Inverting tFALL Figure 8. Inverting www.onsemi.
PAGE 8
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 9. IDD (Static) vs. Supply Voltage Figure 10. IDD (Static) vs. Supply Voltage Figure 11. IDD (No-Load) vs. Frequency Figure 12. IDD (No-Load) vs. Frequency Figure 13. IDD (1 nF Load) vs. Frequency Figure 14. IDD (1 nF Load) vs. Frequency www.onsemi.
PAGE 9
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 15. IDD (Static) vs. Tem perature Figure 16. IDD (Static) vs. Tem perature Figure 17. Input Thresholds vs. Supply Voltage Figure 18. Input Thresholds vs. Supply Voltage Figure 19. Input Thresholds % vs. Supply Voltage www.onsemi.
PAGE 10
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 20. CMOS Input Thresholds vs. Tem perature Figure 21. TTL Input Thresholds vs. Tem perature Figure 22. UVLO Thresholds vs. Tem perature Figure 23. UVLO Hysteresis vs. Tem perature Figure 24. Propagation Delay vs. Supply Voltage Figure 25. Propagation Delay vs. Supply Voltage www.onsemi.
PAGE 11
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 26. Propagation Delay vs. Supply Voltage Figure 27. Propagation Delay vs. Supply Voltage Figure 28. Propagation Delay vs. Tem perature Figure 29. Propagation Delay vs. Tem perature Figure 30. Propagation Delay vs. Tem perature Figure 31. Propagation Delay vs. Tem perature www.onsemi.
PAGE 12
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 32. Fall Tim e vs. Supply Voltage Figure 33. Rise Tim e vs. Supply Voltage Figure 34. Rise and Fall Tim e vs. Tem perature Figure 35. Rise / Fall Waveform s w ith 1 nF Load Figure 36. Rise / Fall Waveform s w ith 10 nF Load www.onsemi.
PAGE 13
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted. Figure 37. Quasi-Static Source Current w ith V DD=12 V Figure 38. Quasi-Static Sink Current w ith V DD=12 V Figure 39. Quasi-Static Source Current w ith V DD=8 V Figure 40. Quasi-Static Sink Current w ith V DD=8 V VDD 470µF Al. El. 4.7µF ceramic Current Probe LECROY AP015 IOUT IN 1kHz 1µF ceramic VOUT CLOAD 0.1µF Figure 41. Quasi-Static IOUT / V OUT Test Circuit www.onsemi.
PAGE 14
Input Thresholds The FAN3100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industry-standard TTL logic thresholds, independent of the V DD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for w hich a voltage over 2 V is considered logic HIGH.
PAGE 15
The FAN3100 incorporates fast-reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10 ns to over 100 ns. The follow ing layout and connection guidelines are strongly recommended:      Keep high-current output and pow er ground paths separate from logic input signals and signal ground paths. This is especially critical w hen dealing w ith TTL-level logic thresholds.
PAGE 16
At pow er up, the driver output remains LOW until the V DD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises w ith V DD until steady-state V DD is reached. The non-inverting operation illustrated in Figure 47 show s that the output remains LOW until the UVLO threshold is reached, then the output is in-phase w ith the input. VDD Turn-on Threshold IN- IN+ OUT Figure 47.
PAGE 17
VIN ENABLE Active LOW FAN3100 IN+ PWM AGND VDD 1 6 2 5 3 4 INPGND OUT Figure 49. Forw ard Converter, Prim ary-Side Gate Drive (MLP Package Show n) Q1 VIN T2 T1 D1 VDD VSEC D2 FAN3100 PWM Q2 CC 0.1µF Figure 50. Driver for Tw o-Transistor Forw ard Converter Gate Transform er VIN Q1 T1 D1 PWM Control/ Isolation SR L VOUT Q5 VSEC D2 Q3 Q2 VDRV ISOLATION FAN3100 Figure 51. Secondary Synchronous Rectifier Driver VDD R FAN3100C IN OUT C Delay IN OUT Figure 52.
PAGE 18
Part Num ber Type Gate Drive (11) (Sink/Src) Input Threshold Logic Package FAN3100C Single 2A +2.5 A / -1.8A CMOS Single Channel of Tw o-Input/One-Output SOT23-5, MLP6 FAN3100T Single 2A +2.5 A / -1.8A TTL Single Channel of Tw o-Input/One-Output SOT23-5, MLP6 FAN3226C Dual 2 A +2.4 A / 1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3226T Dual 2 A +2.4 A / 1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227C Dual 2 A +2.4 A / 1.
PAGE 19
2.0 0.05 C A 1.72 1.68 B 2X 6 4 0.15 2.0 1.21 2.25 0.90 0.52(6X) 0.05 C PIN#1 IDENT TOP VIEW 1 2X 3 0.65 0.42(6X) RECOMMENDED LAND PATTERN 0.75±0.05 0.10 C 0.20±0.05 NOTES: 0.08 C SIDE VIEW 0.025±0.025 SEATING PLANE C A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO-229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 2.00±0.05 1.40±0.05 (0.70) (0.20)4X PIN #1 IDENT 1 3 D.
PAGE 20
3.00 2.80 5 SYMM CL 0.95 0.95 A 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 1.90 0.20 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8° 0° 0.55 0.35 0.60 REF SEATING PLANE Figure 54.
PAGE 21
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf.