Data Sheet

ManualsBrandsON SEMICONDUCTOR ManualsFETsMOSFET 1 360 mW

Publication Order Number:

BSS84/D

September-2017, Rev. 2

BSS84 — P-Channel Enhancement Mode Field-Effect Transistor

BSS84

P-Channel Enhancement Mode Field-Effect Transistor

Features

 -0.13 A, -50 V, R

DS(ON)

= 10 Ω at V

= -5 V

 Voltage-Controlled P-Channel Small-Signal

Switch

 High-Density Cell Design for Low R

DS(ON)

 High Saturation Current

Description

This P-channel enhancement-mode field-effect

transistor is produced using ON Semiconductor’s

proprietary, high cell density, DMOS technology.

This very high density process minimizes on-state

resistance and to provide rugged and reliable

performance and fast switching. The BSS84 can

be used, with a minimum of effort, in most

applications requiring up to 0.13 A DC and can

deliver current up to 0.52 A. This product is

particularly suited to low-voltage applications

requiring a low-current high-side switch.

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only. Values are at T

= 25°C unless otherwise noted.

Symbol

Parameter Ratings Unit

DSS

Drain-Source Voltage

−50

GSS

Gate-Source Voltage

±20

Drain Current

(1)

Continuous

−0.13

Pulsed

−0.52

Maximum Power Dissipation

(1)

0.36

Derate Above 25°C

2.9

mW / °C

, T

STG

Operating and Storage Junction Temperature Range

−55 to +150 °C

Maximum Lead Temperature for Soldering

Purposes, 1/16” from Case for 10 Seconds

300

°C

Thermal Characteristics

θJA

Thermal Resistance, Junction-to-Ambient

(1)

350

°C/W

Note:

1. R

θJA

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference

is defined as the solder mounting surface of the drain pins. R

θJA

is guaranteed by design, while R

θJA

determined by the user's board design.

Scale 1: 1 on letter-size paper.

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

SP BSS84 7’’ 8mm 3000

a) 350°C/W when mounted on a minimum pad

SOT-23

Summary of content (6 pages)

PAGE 1
Features Description   -0.13 A, -50 V, RDS(ON) = 10 Ω at VGS = -5 V   High-Density Cell Design for Low RDS(ON) This P-channel enhancement-mode field-effect transistor is produced using ON Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process minimizes on-state resistance and to provide rugged and reliable performance and fast switching. The BSS84 can be used, with a minimum of effort, in most applications requiring up to 0.
PAGE 2
Symbol Parameter Conditions Min. Typ. Max. Unit Off Characteristics BVDSS Drain–Source Breakdown Voltage ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient IDSS Zero Gate Voltage Drain Current IGSS BVDSS Gate–Body Leakage.
PAGE 3
1 2 -4.5V -3.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) VGS = -5V 0.8 0.6 -3.0V 0.4 -2.5V 0.2 0 1.8 VGS=-3.0V 1.6 1.4 -3.5V 1.2 1 2 3 4 5 -5.0V 0 0.2 0.4 0.6 0.8 1 -VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Drain Current and Gate Voltage 1.8 5 ID = -0.10A VGS = -5V ID = -0.05A RDS(ON), ON-RESISTANCE (OHM) 1.6 1.4 1.2 1 0.8 0.6 0.
PAGE 4
100 VDS = -8V ID = -0.10A f = 1 MHz VGS = 0 V -25V 4 80 CAPACITANCE (pF) -30V 3 2 1 CISS 60 40 20 COSS CRSS 0 0 0 0.2 0.4 0.6 0.8 1 0 10 Qg, GATE CHARGE (nC) 20 30 40 50 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics P(pk), PEAK TRANSIENT POWER (W) 5 SINGLE PULSE RθJA = 350캜 /W TA = 25캜 4 3 2 1 0 0.01 0.1 1 10 100 t1, TIME (sec) Figure 9.
PAGE 5
SOT-23 3L Figure 12. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE www.onsemi.
PAGE 6
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