Data Sheet
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2
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Truth Table
Note:
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) state.
Pin Names Description
D
1
, D
2
Data Inputs
CK
1
, CK
2
Clock Pulse Inputs
CLR
1
, CLR
2
Direct Clear Inputs
PR
1
, PR
2
Direct Preset Inputs
Q
1
, Q
1
, Q
2
, Q
2
Output
Inputs Outputs
FunctionCLR PR DCK
Q Q
LHXX LHClear
HLXX HLPreset
LL
X
XH
(1)
H
(1)
HHL
L H
HHH H L
HHX Q
n
Q
n
No Change