Data Sheet

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74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Publication Order Number:

74VHC74/D

Components Industries, LLC.

August-2017, Rev. 2

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

Features

■

High Speed: f

MAX

= 170MHz (typ.) at T

= 25°C

■

High noise immunity: V

NIH

= V

NIL

= 28% V

(min.)

■

Power down protection is provided on all inputs

■

Low power dissipation: I

= 2µA (max.) at T

= 25°C

■

Pin and function compatible with 74HC74

General Description

The VHC74 is an advanced high speed CMOS Dual

D-Type Flip-Flop fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar

to equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The signal level applied to

the D input is transferred to the Q output during the posi-

tive going transition of the CK pulse. CLR

and PR are

independent of the CK and are accomplished by setting

the appropriate input LOW.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Pack

age

Number Package Description

74VHC74M M14A 14-Lead Small Outline Integr

ated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Summary of content (6 pages)

PAGE 1
Features General Description ■ High Speed: fMAX = 170MHz (typ.) at TA = 25°C The VHC74 is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse.
PAGE 2
Logic Symbol IEEE/IEC Truth Table Pin Description Pin Names Inputs Description Outputs CLR PR D CK Q Q Clock Pulse Inputs L H X X L H Clear Direct Clear Inputs H L X X H L Preset PR1, PR2 Direct Preset Inputs L L X X H(1) H(1) Q1, Q1, Q2, Q2 Output H H L L H H H H H L H H X Qn Qn D1, D2 Data Inputs CK1, CK2 CLR1, CLR2 Function No Change Note: 1.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.
PAGE 4
TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions 1.50 3.0–5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage Min. 3.0 LOW Level Output Voltage Min. IOH = –50µA 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 3.0 IOH = –4mA 2.58 2.48 IOH = –8mA 3.94 3.80 2.0 VIN = VIH or VIL IOL = 50µA 4.5 3.0 4.5 IOL = 8mA V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA V 0.3 x VCC 1.9 4.5 3.0 Units V 0.50 0.
PAGE 5
TA = –40°C to +85°C TA = 25°C Symbol fMAX Parameter Maximum Clock Frequency VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CK-Q, Q) 3.3 ± 0.3 5.0 ± 0.5 tPLH, tPHL Propagation Delay Time (CLR, PR -Q, Q) 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Conditions CL = 15pF Min. Typ. 80 125 Max. Min. Max. 70 CL = 50pF 50 75 45 CL = 15pF 130 170 110 CL = 50pF 90 115 75 MHz CL = 15pF 6.7 11.9 1.0 14.0 CL = 50pF 9.2 15.4 1.
PAGE 6
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