Data Sheet

©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC164 Rev. 1.4.0 2
74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register
Connection Diagram
Pin Description
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the
logical AND of the two data inputs (A • B) that existed
before the rising clock edge. A LOW level on the Master
Reset (MR
) input overrides all other inputs and clears
the register asynchronously, forcing all Q outputs LOW.
Logic Symbol
Function Table
H = HIGH Voltage Levels
L = LOW Voltage Levels
X = Immaterial
Q = Lower case letters indicate the state of the
referenced input or output one setup time prior to
the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Pin
Names
Description
A, B Data Inputs
CP Clock Pulse Input (Active Rising Edge)
MR
Master Reset Input (Active LOW)
Q
0
–Q
7
Outputs
Operating
Mode
Inputs Outputs
MR
ABQ
0
Q
1
–Q
7
Reset (Clear) L X X L L–L
Shift H L L L Q
0
–Q
6
HLHL Q
0
–Q
6
HHL L Q
0
–Q
6
HHHH Q
0
–Q
6