Data Sheet

©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVX74 Rev. 1.4.0 2
74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Connection Diagram
Pin Description
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q
0
(Q
0
) = Previous Q(Q
) before LOW-to-HIGH Transition
of Clock
Pin Names Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
Inputs Outputs
S
D
C
D
CP D Q Q
LHXXHL
HLXXLH
LLXXHH
HH HHL
HH L LH
HHLXQ
0
Q
0