Data Sheet
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1.6 5
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics (Continued)
Switching Characteristics (V
CC
= 5 V, I
F
= 7.5 mA, T
A
= -40°C to +85°C unless otherwise specified)
Notes:
5. t
PHL
– Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. t
PLH
– Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
7. t
R
– Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
8. t
F
– Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
9. t
EHL
– Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. t
ELH
– Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
11. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
cm
/dt on the leading edge
of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic high state (i.e., V
O
> 2.0 V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV
cm
/dt on the trailing edge
of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic low state (i.e., V
O
< 0.8 V).
Symbol Parameter Device Test Conditions Min. Typ. Max. Unit
t
PHL
Propagation Delay
Time to Logic LOW
All
R
L
= 350 Ω, C
L
= 15 pF,
T
A
= 25°C
(5)
(Fig. 14)
25 40 75
ns
R
L
= 350 Ω, C
L
= 15 pF
(5)
(Fig. 14)
100
t
PLH
Propagation Delay
Time to Logic HIGH
All
R
L
= 350 Ω, C
L
= 15 pF
,
T
A
= 25°C
(6)
(Fig. 14)
20 40 75
ns
R
L
= 350 Ω, C
L
= 15 pF
(6)
(Fig. 14)
100
|t
PHL
–t
PLH
| Pulse Width Distortion All
R
L
= 350 Ω, C
L
= 15 pF
(Fig. 14)
135ns
t
R
Output Rise Time
(10% to 90%)
All
R
L
= 350 Ω, C
L
= 15 pF
(7)
(Fig. 14)
30 ns
t
F
Output Fall Time
(90% to 10%)
All
R
L
= 350 Ω, C
L
= 15 pF
(8)
(Fig. 14)
10 ns
t
EHL
Enable Propagation
Delay Time to Output
LOW Level
Single Channel
V
EH
= 3.5 V, R
L
= 350 Ω,
C
L
= 15 pF
(9)
(Fig. 15)
15 ns
t
ELH
Enable Propagation
Delay Time to Output
HIGH Level
Single Channel
V
EH
= 3.5 V, R
L
= 350 Ω,
C
L
= 15 pF
(10)
(Fig. 15)
15 ns
|CM
H
|
Common Mode
Transient Immunity
at Logic High
6N137M,
HCPL2630M
I
F
= 0 mA, V
CM
= 50 V
PEAK
,
R
L
= 350 Ω, T
A
= 25°C
(11)
(Fig. 16)
10,000
V/µs
HCPL2601M,
HCPL2631M
5000 10,000
HCPL2611M
I
F
= 0 mA, V
CM
= 400 V
PEAK
,
R
L
= 350 Ω, T
A
= 25°C
(11)
(Fig. 16)
10,000 15,000
|CM
L
|
Common Mode
Transient Immunity
at Logic Low
6N137M,
HCPL2630M
V
CM
= 50 V
PEAK
,
R
L
= 350 Ω, T
A
= 25°C
(11)
(Fig. 16)
10,000
V/µs
HCPL2601M,
HCPL2631M
5000 10,000
HCPL2611M
V
CM
= 400 V
PEAK
,
R
L
= 350 Ω, T
A
= 25°C
(11)
(Fig. 16)
10,000 15,000