Data Sheet

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL26XXM Rev. 1.6
January 2016
Dual-Channel: HCPL2630M, HCPL2631M — 8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
8-Pin DIP High-Speed 10 MBit/s Logic Gate Optocouplers
Features
• Very High Speed – 10 MBit/s
• Superior CMR – 10 kV/µs
• Fan-out of 8 Over -40°C to +85°C
• Logic Gate Output
• Strobable Output
• Wired OR-open Collector
• Safety and Regulatory Approvals
– UL1577, 5,000 VAC
RMS
for 1 Minute
– DIN EN/IEC60747-5-5
Applications
• Ground Loop Elimination
• LSTTL to TTL, LSTTL or 5 V CMOS
• Line Receiver, Data Transmission
• Data Multiplexing
• Switching Power Supplies
• Pulse Transformer Replacement
• Computer-peripheral Interface
Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common mode
rejection of typically 10 kV/µs. The HCPL2601M and
HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Schematics Package Outlines
1
2
3
4 5
6
7
8
N/C
_
V
CC
V
E
V
O
GND
+
N/C
V
F
1
2
3
4 5
6
7
8
+
_
V
F1
V
CC
V
01
V
02
GND
V
F2
_
+
HCPL2630M,
HCPL2631M
6N137M
,
HCPL2601M,
HCPL2611M
A 0.1µF bypass capacitor must be connected between pins 8 and 5
(1)
.
Truth Table (Positive Logic)
Input Enable Output
H H L
L H H
H L H
L L H
H NC L
L NC H
8
8
1
8
1
1
8
1
Figure 1. Schematics
Figure 2. Package Options