Datasheet

CJ1 series CPU Units 155
Programmable
Controllers
Note: The available data memory capacity is the sum of the Data Memory (DM) and the Extended Data Memory (EM).
Common Specifications
Note: The CJ1G-CPU43H/42H support a maximum of 2 Expansion Racks with a total maximum of 30 Units.
The CJ1M-CPU13/23 support only 1 Expansion Rack with a total maximum of 20 Units (19 Units for CJ1M-CPU13-ETN).
The CJ1M-CPU11/12/21/22 do not support Expansion Racks and support a total maximum of 10 Units
(9 Units for CJ1M-CPU11/CPU12-ETN).
CPU Units
Model I/O bits Program
capacity
Data memory capacity
(See note.)
LD instruction
processing speed
Built-in ports Options Built-in I/O
CJ1H-CPU67H 2,560 bits (Up to
3 Expansion Racks)
250 kSteps 448 kWords
(DM: 32 kWords,
EM: 32 kWords x 13 banks)
0.02 µs Peripheral port
and RS-232C
port. -ETN
models include
a 100Base-Tx
Ethernet port.
Memory Cards CPU##P
models
include
Process
Control
Engine
CJ1H-CPU66H 120 kSteps 256 kWords
(DM: 32 kWords,
EM: 32 kWords x 7 banks)
CJ1H-CPU65H 60 kSteps 128 kWords
(DM: 32 kWords,
EM: 32 kWords x 3 banks)
CJ1G-CPU45H
CJ1G-CPU45P
1,280 bits (Up to
3 Expansion Racks)
0.04 µs
CJ1G-CPU44H
CJ1G-CPU44P
30 kSteps 64 kWords
(DM: 32 kWords,
EM: 32 kWords x 1 bank)
CJ1G-CPU43H
CJ1G-CPU43P
960 bits (Up to
2 Expansion Racks)
20 kSteps
CJ1G-CPU42H
CJ1G-CPU42P
10 kSteps
CJ1M-CPU13
CJ1M-CPU13-ETN
640 bits (Only
1 Expansion Rack)
20 kSteps 32 kWords
(DM: 32 kWords,
EM: None)
0.10 µs
CJ1M-CPU12
CJ1M-CPU12-ETN
320 bits
(No Expansion Rack)
10 kSteps
CJ1M-CPU11
CJ1M-CPU11-ETN
160 bits
(No Expansion Rack)
5 kSteps
CJ1M-CPU23 640 bits (Only
1 Expansion Rack)
20 kSteps Inputs: 10
Outputs: 6
CJ1M-CPU22 320 bits
(No Expansion Rack)
10 kSteps
CJ1M-CPU21 160 bits
(No Expansion Rack)
5 kSteps
Item Specification
Control method Stored program
I/O control method Cyclic scan and immediate processing are both possible.
Programming Ladder diagram
Instruction length 1 to 7 steps per instruction
Ladder instructions Approx. 400 (3-digit function codes)
Execution time Basic instructions: 0.02 µs min.; Special instructions: 0.04 µs min.
Overhead time CJ1G/H-CPU@@H: 0.3 ms
CJ1G-CPU@@P: 0.3ms
CJ1M-CPU@@(-ETN): 0.5 ms
CJ1M-CPU@1(-ETN): 0.7 ms
Unit connection method No backplane (Units joined together with connectors.)
Mounting method DIN rail mounting (screw mounting not supported)
Maximum number of connectable Units Per CPU or Expansion Rack: 10 Units max. (Basic I/O Units, Special I/O Units, or CPU Bus Units)
Total per PLC: 10 Units on CPU Rack and 10 Units each on 3 Expansion Racks = 40 Units max. (See note.)
Maximum number of Expansion Racks 3 max. (A CJ-series I/O Control Unit is required on the CPU Rack and a CJ-series I/O Interface Unit is required on each
Expansion Rack.) (See note.)
Number of tasks 288 (cyclic tasks: 32, interrupt tasks: 256)
Interrupt tasks can be defined as cyclic tasks to create cyclic interrupt tasks.
Note: 1. Cyclic tasks are executed each cycle and are controlled with TKON(820) and TKOF(821) instructions.
2. The following 4 types of interrupt tasks are supported:
Power OFF interrupt task: 1 max.
Scheduled interrupt tasks: 2 max.
I/O interrupt tasks: 32 max.
External interrupt tasks: 256 max.
Interrupt types Scheduled Interrupts:Interrupts generated at a time scheduled by CPU Unit’s built-in timer
(Interval: 1 to 9,999 ms or 10 to 99,990 ms; also 0.5 to 999.9 ms with CJ1M)
I/O interrupt tasks:Interrupts from Interrupt Input Units or, with CJ1M, built-in I/O
Power OFF Interrupts:Interrupts executed when CPU Unit’s power is turned OFF
External interrupt tasks:Interrupts from Special I/O Units and CPU Bus Units
Calling subroutines from multiple tasks Supported using global subroutines.
Functions Blocks (CPU Ver. 3.0 or higher) Languages supported for use in function block programming: Ladder program language and IEC 61131-3 Structured Text.
Y201-EN2-03.book Seite 155 Donnerstag, 30. März 2006 1:52 13