User Guide

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¬Smart Phones
Video Conferencing
PC Multimedia
Applications
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automatic black level calibration (ABLC)
programmable controls for:
- frame rate
- mirror and flip
- binning
- cropping
- windowing
support for dynamic DPC
supports output formats:
- 10-bit RGB 4C non-HDR
- 10-bit RGB Bayer non-HDR
supports horizontal and
vertical subsampling
supports typical images sizes:
- 9248 x 6944
- 7680 x 4320
- 4624 x 4320
- 3840 x 2160
- 1920 x 1080
- 1280 x 720
standard serial SCCB interface
up to 4-lane MIPI TX interface
with speed up to 3.0 Gbps/lane
2/3 trio CPHY interface,
up to 2.45 Gsps/trio
supports type 2 2x2 ML PDAF
4-cell support:
- 4-cell binning
- 4-cell full
HDR support:
stagger HDR 2/3 exposure timing
on-chip 4-cell to Bayer converter
three on-chip phase lock loops (PLLs)
programmable I/O drive capability
built-in temperature sensor
0.702 µm pixel
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Product Features
¬ OV64B40-GA5A-002A
(color, chip probing, 150 µm backgrinding, reconstructed wafer with good die)
Ordering Information
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active array size: 9248 x 6944
maximum image transfer rate:
- 9248 x 6944: 15 fps
power supply:
- core: 1.1V
- analog: 2.8V
- I/O: 1.8V
power requirements:
- active: 647 mW (64MP @ 15 fps)
- standby: <10 µA
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temperature range:
- operating: -30°C to +85°C junction
temperature
- stable: 0°C to +60°C junction
temperature
output formats: 10-bit RGB RAW
lens size: 1/2"
lens chief ray angle: 34.55° non-linear
scan mode: progressive
pixel size: 0.702 µm x 0.702 µm
image area:
6514.56 µm x 4897.152 µm
Technical Specifications
Version 1.2, June 2021
OmniVision reserves the right to make changes to their products or to discontinue any product or
service without further notice. OmniVision, the OmniVision logo and PureCel are registered
trademarks of OmniVision Technologies, Inc. All other trademarks are the property of their
respective owners.
4275 Burton Drive
Santa Clara, CA 95054
USA
Tel: + 1 408 567 3000
Fax: + 1 408 567 3001
www.ovt.com
OV64B
Functional Block Diagram
OV64B40
image sensor core image
sensor
processor
image
interface
column
sample/hold
row select
PLLs PLL
control register bank
timing generator and
system control logic
SCCB interface
gain
control
XVCLK
XSHUTDOWN
PWDNB
TM
STROBE
SCL
SID/SID2
SDA
GPIO[1:0]
HREF
VSYNC
FSIN
MCP/N
MDP/N[3:0]
or
MC0A, MC0B, MC0C
MC1A, MC1B, MC1C
MC2A, MC2B, MC2C
temperature
sensor
image
array
AMP
10-bit
ADC
FIFO
ISP
MIPI