Owner's manual

Chapter 3: Architecture
39
Counter-timers
Depending on your PowerDAQ DIO board operation mode, the board
can support up to the three DSP based 24-bit counter/timers with
maximum count rate up to the 33 MHz for internal base clock and 16.5
MHz for the external clock. The minimum count rate is 0.00002 Hz for
the internal clock and has no bottom limit (but still require relatively
sharp, no longer than 1 ms, falling edge) for the external clock.
The software does not inform you directly which
counter/timers are available. To check the current
status of the timer you may check M_TE bit in the
timer status register using the _PdDSPRegRead
function.
Calibration and startup configuration
There is a critical requirement for the digital I/O board to have a
predictable output state during the start-up process. PowerDAQ DIO
boards provide an even more flexible way to define a start-up state of
every DIO channel on the board. To do so, start-up values along with
some other critical data are stored into on-board EEPROM. Those values
are loaded approximately 10mS after the rising edge of the system
reset signal. Also, for the PXI board, configuration of the PXI lines is
also stored into EEPROM. EEPROM has user accessible values and user
may potentially store some non-volatile data using applications. Because
EEPROM is a life-critical subsystem there are no examples provided for
such an access. Please consult factory if you consider EEPROM usage in
your applications.
TIP