(1*,1((5,1* ,1& DAQ-12 Data Acquisition Adapter For 16 bit ISA compatible machines Users Manual INTERFACE CARDS FOR PERSONAL COMPUTERS OMEGA ENGINEERING, INC. One Omega Drive P.O. Box 4047 Stamford, CT 06907-4047 http://www.dasieee.com TEL: (203) 359-1660 FAX: (203) 359-7700 Toll free: 1-800-826-6342 E-mail: das@omega.
WARRANTY/DISCLAIMER OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship for a period of 13 months from the date of purchase. OMEGA warranty adds an additional one (1) month grace period to the normal one (1) year product warranty to cover shipping and handling time. This ensures that OMEGA’s customers receive maximum coverage on each product. If the unit should malfunction, it must be returned to the factory for evaluation.
Declaration of Conformity Manufacturer's Name: Omega Engineering, Inc.
OMEGAnet On-line Service: http://www.omega.com Internet e-mail: info@omega.com Servicing North America: USA: ISO 9001 Certified Canada: One Omega Drive, Box 4047 Stamford, CT 06907-0047 Tel: (203) 359-1660 E-mail: info@omega.com 976 Bergar Laval (Quebec) H7L 5A1 Tel: (514) 856-6928 E-mail: info@omega.
United Kingdom: ISO 9002 Certified One Omega Drive, River Bend Technology Drive Northbank, Irlam, Manchester M44 5EX, England Tel: 44 (161) 777-6611 FAX: 44 (161) 777-6622 Toll Free in England: 0800-488-488 E-mail: info@omega.co.uk It is the policy of OMEGA to comply with all worldwide safety and EMC/EMI regulations that apply. OMEGA is constantly pursuing certification of it’s products to the European New Approach Directives. OMEGA will add the CE mark to every appropriate device upon certification.
Table of Contents 1. Introduction ......................................................... 8 1.1 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 DAQ-12 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. Circuit Board Description and Configuration .............. 2.1 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures and Tables Figure 2-1. Jumper J1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-2. Jumper J7 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-3. Jumper J6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-4. Jumper J4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. Introduction The DAQ-12 is a high speed data acquisition adapter for IBM AT and compatible machines offering eight differential analog input channels with 16-bit resolution, two analog output channels with 12-bit resolution and four digital input/output lines.
1.2 DAQ-12 Specifications Bus Interface: ISA 16-bit I/O Address Range: 0000H - FFFFH Interrupt Levels: IRQ 2, 3, 4. 5, 6, 7, 10, 11, 12, 14, 15 DMA Levels: DRQ 5, 6, 7 DACK 5, 6, 7 Power Requirements: Power Supply I(t) I(ms) -5 volts --- --- +5 volts 1069.0 mA 1204.9mA -12 volts --- --- +12 volts 374.9 mA 491.
2. Circuit Board Description and Configuration The base address of the DAQ-12 is selected using switches SW1 and SW2. The operating mode of the DAQ-12 is controlled by jumpers J1 through J7, while DMA and interrupt selections are set with jumpers J8 through J11. Connections to external equipment are made through the high density 62-pin connector CN1. 2.
The amplifier stage of the A/D converter circuit performs two functions: (1) amplifies low level input signals and (2) converts this input signal into a voltage range acceptable to the A/D converter. Seven gain levels are software selectable for the amplifier stage of the A/D circuit. To support high level input signals, the DAQ-12 provides input gain selections of 1, 2, 4 and 8. For signals requiring greater amplification, the DAQ-12 provides input gains of 1, 10, 100 and 500.
Table 2-1 details the available gain settings and resulting input ranges for the various input configurations. Note that the 'gain byte' field in Table 2-1 is the value written to the DAQ-12's gain control register. (* indicates unipolar mode not available with gain of ½ ). Maximum Input Voltage Unipolar / Bipolar +10/±5 +1/±0.5 +0.1/±0.05 +0.02/±0.01 +10/±5 +5/±2.5 Amplifier Gain 1 10 100 500 1 2 J7 --1-2 1-2 1-2 1-2 1-2 1-2 Gain Byte (HEX) --00 01 02 03 80 81 +2.5/±1.25 +1.25/±0.
The final stage of the A/D converter circuit is the A/D converter IC. The converter must be configured for unipolar or bipolar input voltages as shown in Figure 2-3. When configured for unipolar operation, the analog input multiplied by the gain setting must be in the range of 0 volts (analog ground) to +10 volts. When configured for bipolar operation, the analog input multiplied by the gain setting must be in the range of -5 volts to +5 volts.
Voltage -5 -2.5 0 2.5 5 10 0000 0000 0000 0000 Unipolar Code n/a n/a 0000 0000 0100 0000 1000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 Bipolar Code 1000 0000 1100 0000 0000 0000 0100 0000 0111 1111 n/a 0000 0000 0000 0000 1111 Table 2-2. A/D Conversion Format Examples NOTE: The 'voltage' column is the voltage applied to the A/D converter. This voltage is equivalent to the input voltage multiplied by the amplifier gain. 2.
The D/A converter channels may also be operated in unipolar mode: 0 to +5 volts, or bipolar mode: -5 to +5 volts. The output mode is selected using jumper J5 as shown in Figure 2-5. In addition, a gain selection jumper is provided to select an output gain of 1 or 2. When using an external voltage reference, this gain can be used to amplify the D/A output for small reference voltages. WARNING: When the internal voltage reference is used,the D/A gain MUST be set to the gain = 1 position.
2.3 Digital Input/Output The DAQ-12 offers four bits of digital output and four bits of digital input for control/monitoring of external digital devices. The four digital output lines are LS TTL compatible and will initialize low (0 volts) on power-up. The four digital inputs are also LS TTL compatible. There is no termination provided on the digital input lines and a read of an unused digital input will result in an indeterminate value. 2.
2.5 Clock Selection The DAQ-12 is equipped with a programmable clock circuit to produce data sampling rates independent from the clock rate of the host computer. An onboard 8254 programmable interval timer, with a 10 MHz clock input and either two or three cascaded 16-bit timers, provides the sampling rate. This enables the sampling rate to be adjusted from 5 us between samples to almost a year between samples, in as small as 100ns increments.
2.5.1 Internal Clock Sampling rates for the internal clock can be calculated using the following equation: t = 100ns * [N1*N2] or f = 10MHz / [N1*N2] where N1 is the low 16-bits of the clock divider and N2 is the high 16-bits of the clock divider. The following criteria must be met when selecting values for N1 and N2: 2 < N1 < 65,535 2 < N2 < 65,535 N1 * N2 > 50 Using the equations above, the minimum and maximum data sampling rates for the internal clock can be calculated.
When configured for a 48-bit divider, the first sampling period will be slightly longer than the others because the first clock period is required to load the initial value of the multi-function timer. The following equation calculates the additional time of the first period: t add = 100ns * [N1 * N2] To minimize the amount of additional time required for the first sample, select clock dividers such that N1 and N2 are as small as possible and N3 is as large as possible.
When the multi-function timer is used as a pre-divider, the frequency of the external clock input may be varied from DC to 10 MHz as long as the high portion of the clock is at least 30ns and the low portion is at least 50ns. Except for the first period, the sampling rate of the DAQ-12 will be the external clock frequency divided by the count value written to the multi-function timer.
2.7 Direct Memory Access Direct Memory Access (DMA) transfers provide a way of transferring data from the DAQ-12's A/D converter into the personal computer's memory without using the Central Processing Unit (CPU). DMA capability enables other system software to be executed while data is being input from the DAQ-12. The DAQ-12 actually implements two DMA channels. The advantage of having two DMA channels is that one channel can be transferring data while the second channel is being programmed.
2.8 Interrupts The DAQ-12 is capable of generating an interrupt from one of four sources: 1. End of conversion signal 2. DMA terminal count 3. Multi-function timer output 4. External interrupt input The interrupt source is software selected through the DAQ-12 control word register. The interrupt level is selected using the jumpers J10 and J11 as shown in Figure 2-11. J11 IRQ 7 IRQ 6 IRQ 5 IRQ 4 IRQ 3 IRQ 2 IRQ 10 IRQ 11 IRQ 12 IRQ 15 IRQ 14 J10 Factory default = IRQ 5 Figure 2-11.
3. External Connections The DAQ-12 is equipped with a high density 62-pin connector as shown in Figure 3-1.
CHx-, CHx+ : Analog inputs to the analog to digital converter. When using differential input mode, eight input channels are available (CH0+ to CH7+). When using single-ended inputs, 16 channels are available (CH0+ to CH15+). The first eight channels are input through the connections marked CH0+ to CH7+ and the second eight channels through CH0to CH7-. AOUT0, AOUT1: Analog outputs from the digital to analog converters. Polarity and maximum amplitude depend on the jumper settings and voltage references.
4. Register Description and Programming The DAQ-12 uses 16 consecutive I/O address locations in the range 0 to FFFFH. The card utilizes these addresses for the registers listed in Table 4-1. (* indicates registers located in 8254 counter).
INT2, INT1 and INT0 control the DAQ-12 interrupt source. INT2 INT1 INT0 DESCRIPTION 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 Interrupt disabled Interrupt timer 2 Interrupt on terminal count External interrupt Interrupt on end of conversion DMAEN - enables / disables DMA. When set, logic 1, DMA transfers are enabled. DMACT - enables the multi-channel DMA capability of the DAQ-12. When set, logic 1, a terminal count on the active DMA channel causes DMA transfers to begin on the "stand-by" channel.
VALID - when set, logic 1, indicates at least one data sample was lost because it was read by the personal computer before the next sample was converted. Data was lost because the sampling rate was too fast for the computer to acquire the data. VALID is reset by writing to the start conversion register. CHSL2, CHSL1, CHSL0 - select the multiplexer channel for the analog input signal. (* denotes only available in single ended input mode).
4.1.4 D/A Converter 0 Register An output to this register causes the lower twelve bits of data to be converted to an analog output on D/A converter channel 0. The four most significant bits of data are ignored. This register is 16-bit write only. 4.1.5 D/A Converter 1 Register An output to this register causes the lower twelve bits of data to be converted to an analog output on D/A converter channel 1. The four most significant bits of data are ignored. This register is 16-bit write only.
4.2 Programming the 8254 Counter/Timer This section provides programming information for the 8254 counter/timer as implemented on the DAQ-12. For more details on the 8254, consult the Intel Micro-processor and Peripheral Handbook. To program any of the counters contained in the 8254 counter/timer, three steps are required: 1. Write the configuration byte to the 8254 mode select/status register. This byte sets the operating mode of the selected counter. 2.
Counter 1 - Clock rate register (high word) operating mode: minimum count value: configuration byte: Example: 2 2 0 / 1 / 1 / 1 / 0 / 1 / 0 / 0 = 74H Program the value 13A4H into the high word of the clock rate register. output 74H to base_address + 0FH output A4H to base_address + 0DH output 13H to base_address + 0DH Example: Program the value FFFFH into the high word of the clock rate register.
DAQ-12 Users Manual Version 2.20 January 28, 1999 Part No.
